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VR4102 Datasheet(PDF) 646 Page - NEC |
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VR4102 Datasheet(HTML) 646 Page - NEC |
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646 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 646 SUSPEND Suspend SUSPEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 SUSPEND 1 0 0 0 1 0 31 26 25 6 5 0 619 6 CO 1 1 24 Format: SUSPEND Description: SUSPEND instruction starts mode transition from Fullspeed mode to Suspend mode. When the SUSPEND instruction finishes the WB stage, the VR4102 wait by the SysAD bus is idle state, after then the internal clocks including the TClock will shut down, thus freezing the pipeline. The PLL, Timer/Interrupt clocks and MasterOut, will continue to run. Once the VR4102 is in Suspend mode, any interrupt, including the internally generated timer interrupt, NMI, Soft Reset and Cold Reset will cause the VR4102 to exit Suspend mode and to enter Fullspeed mode. Operation: 32, 64 T: T+1: Suspend operation () Exceptions: Coprocessor unusable exception Remark Refer to Chapter 15 for details about the operation of the peripheral units at mode transition. |
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