SC3200 datasheet(445/447 Pages) AMD

445 / 447 page

AMD Geode™ SC3200 Processor Data Book

445

Appendix A: Data Book Revision History

Revision 5.1

Table A-2. Edits to Current Revision

Section

Revision

Section 1.0

"AMD Geode™

SC3200

Processor"

• Section 1.2 "Features" on page 14:

— Other Features: Modified Voltages sub-bullets for clarification purposes.

Section 2.0

“Architecture

Overview”

• No changes.

Section 3.0

“Signal

Definitions”

• Section 3.4.6 "PCI Bus Interface Signals" on page 68:

— Rewrote SERR# description, was wrong.

• Section 3.4.10 "Universal Serial Bus (USB) Interface Signals" on page 76:

— Changed footnote to say “A 15 K

Ω pull-down resistor is required on all ports (even if unused).”

Section 4.0

"General

Configuration

Block"

• Table 4-7 "Strapped Core Clock Frequency" on page 101:

— Added note: “Note: Not all speeds are supported. For information on supported speeds, see

Section A.1 "Order Information" on page 443.”

Section 5.0

“SuperI/O

Module”

• No changes.

Section 6.0

"Core Logic

Module"

• Section 6.2.6.1 "DMA Controller" on page 168:

— Added text in parenthesis to first bullet. Now reads as “Standard seven-channel DMA support

(Channels 5 through 7 are not supported).”

— DMA Channels subsection: Added last sentence to last paragraph “DMA Channels 5 through 7

are not supported.”

• Section 6.2.6.3 "Programmable Interrupt Controller" on page 171:

— Added second sentence to first paragraph, “The PIC devices support all x86 modes of opera-

tion except Special Fully Nested mode.”

• Section 6.4.1 "Bridge, GPIO, and LPC Registers - Function 0" on page 206:

— F0 Index 6Ch (ROM Mask Register): Corrected reset value to 0000FFF0h (was listed as

FFF0h). Added note, “Note: Register must be read/written as a DWORD.” Also corrected reset

value and “Width” column in Table 6-14 on page 192 (register summary table).

— F0BAR1+I/O Offset 00h: Rewrote bit descriptions and added note for clarification purposes.

— F0BAR1+Offset 0Ch: Rewrote bit descriptions and added note for clarification purposes.

— F0BAR1+Offset 10h[13]: Changed note. Did say “This bit should not be enabled when using

the internal SuperI/O module and if IO_SIOCFG_IN (F5BAR0+I/O Offset 00h[26:25]) = 11.”

Now says “This bit should not be routed to LPC when using the internal SuperI/O module and if

IO_SIOCFG_IN (F5BAR0+I/O Offset 00h[26:25]) = 10.”

• Section 6.4.2 "SMI Status and ACPI Registers - Function 1" on page 252:

— F1BAR0+I/O Offset 00h[11] and Offset 02h[11]: Clarified that the IRQ2 is from the SIO module

and not an external SIO.

• Section 6.4.3 "IDE Controller Registers - Function 2" on page 273:

— F2 Index 40h and 44h: Removed Format 0 and Format 1 settings for a Fast-PCI clock

frequency of 48 MHz since it is not supported.

• Section 6.4.7 "ISA Legacy Register Space" on page 313:

— Changed register descriptions in Table 6-43 and Table 6-44 to emphasize that DMA Channels

5 through 7 are not supported.

Section 7.0

“Video

Processor

Module”

• No changes.

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