ECE1200 datasheet(25/87 Pages) MICROCHIP

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DS00003093C Draft-page 25

ECE1200

5.0

ENHANCED SERIAL PERIPHERAL INTERFACE (ESPI)

5.1

Introduction

The Intel® Enhanced Serial Peripheral Interface (eSPI) in the ECE1200 is a hard-wired subset of the eSPI functionality,

dedicated to bridging I/O and Memory traffic with LPC, and Serial IRQ traffic. It also implements Virtual Wires, by which

it restores legacy signals and supports new eSPI requirements internally.

5.2

References

Intel Doc #327432, Enhanced Serial Peripheral Interface (eSPI): Interface Base Specification

Intel Doc #562633, Enhanced Serial Peripheral Interface (eSPI) Compatibility Specification

5.3

Terminology

This table defines specialized terms localized to this feature.

TABLE 5-1:

TERMINOLOGY

Term

Definition

System Host

Refers to the external Chipset that originates the I/O and Memory traffic over the

eSPI Interface.

Master / Slave

Following the SPI convention, the System Host is the eSPI Master and the

ECE1200 is the eSPI Slave. The Slave can request the Master’s attention using

the ALERT# functionality, but all traffic is driven by the Master.

Virtual Wire /

Virtual Wire Channel

A Virtual Wire is a 1-bit digital state that is transferred between the System Host

and the ECE1200. Some Virtual Wires are translated to/from physical pins by the

ECE1200. Other Virtual Wires present IRQs to the Host System from the Serial

IRQ feature, participate in handshakes for system power state transitions, or sig-

nal exceptions to the Host System.

The eSPI Virtual Wire Channel is a category of eSPI traffic that is multiplexed

onto the eSPI pins for transferring Virtual Wires.

Peripheral Channel

This is a category of eSPI traffic that is multiplexed onto the eSPI pins for per-

forming I/O and Memory traffic originating from the System Host.

eSPI Configuration Registers

A set of registers that are dedicated to initial low-level setup of the eSPI bus by

the System Host. They are accessible only using the eSPI GET_CONFIGURA-

TION and SET_CONFIGURATION commands, and are separate from the inter-

nal register set that is accessed by I/O traffic.

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