ECE1200 datasheet(58/87 Pages) MICROCHIP

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ECE1200

DS00003093C Draft-page 58

 2018-2021 Microchip Technology Inc.

7.0

TEST MECHANISMS

7.1

Introduction

This device has the following test mechanism:

• XNOR Chain for board connectivity test

7.2

References

No references have been cited for this chapter.

7.3

Terminology

Terms are defined in the text below.

7.4

XNOR Chain

7.4.1

OVERVIEW

The XNOR Chain test mode provides a means to confirm that all ECE1200 pins are in contact with the motherboard

during assembly and test operations.

An example of an XNOR Chain test structure is illustrated below in Figure 7-1, "XNOR Chain Test Structure". When

the XNOR Chain test mode is enabled all pins, except for those listed in Section 7.4.2, "Excluded Pins", are discon-

nected from their internal functions and routed as inputs to the XNOR Chain. This allows a single input pin to toggle

the XNOR Chain output if all other input pins are held high or low. The XNOR Chain output is the pin SUSWARN#.

The tests that are performed when the XNOR Chain test mode is enabled require the board-level test hardware to con-

trol the device pins and observe the results at the XNOR Chain output pin; e.g., as described in Section 7.4.3, "Test

Procedure," on page 59.

FIGURE 7-1:

XNOR CHAIN TEST STRUCTURE

I/O#1

I/O#2

I/O#3

I/O#n

XNOR

Out

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