 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ECE1200 Datasheet(PDF) 56 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
ECE1200 Datasheet(HTML) 56 Page - Microchip Technology |
|
|
56 / 87 page  ECE1200 DS00003093C Draft-page 56 2018-2021 Microchip Technology Inc. 6.11.8 LPC ERROR LOG NON-POSTED REGISTER 6.11.9 LPC ERROR LOG POSTED REGISTER Index F2h of Logical Device 01h Bits Description Type Default Reset Event 7:4 Reserved R 0h - 3 IORM_CHKIDL ‘1’ = An IOCHK# event has occurred while the LPC bus is idle. ‘0’ = No IOCHK# event has occurred during LPC idle, since this bit was last cleared. R/W1C 0 eSPI_RESET 2 IORM_CHK_ACTIVE ‘1’ = An IOCHK# event has occurred during a Non-Posted transfer on LPC (I/O Read or Write, or Memory Read). ‘0’ = No IOCHK# event has occurred during a Non-Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 1 IORM_ABTSYN ‘1’ = An Abort SYNC event has occurred during a Non-Posted transfer on LPC (I/O Read or Write, or Memory Read). ‘0’ = No Abort SYNC event has occurred during a Non- Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 0 IORM_UNCL ‘1’ = An Unclaimed or Invalid SYNC event has occurred during a Non-Posted transfer on LPC (I/O Read or Write, or Memory Read). ‘0’ = No Unclaimed or Invalid SYNC event has occurred during a Non-Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET Index F3h of Logical Device 01h Bits Description Type Default Reset Event 7:3 Reserved R 00h - 2 MW_CHK_ACTIVE ‘1’ = An IOCHK# event has occurred during a Posted transfer on LPC (Memory Write). ‘0’ = No IOCHK# event has occurred during a Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 1 MW_ABTSYN ‘1’ = An Abort SYNC event has occurred during a Posted transfer on LPC (Memory Write). ‘0’ = No Abort SYNC event has occurred during a Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 0 MW_UNCL ‘1’ = An Unclaimed or Invalid SYNC event has occurred during a Posted transfer on LPC (Memory Write). ‘0’ = No Unclaimed or Invalid SYNC event has occurred during a Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
