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ECE1200 Datasheet(PDF) 57 Page - Microchip Technology |
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ECE1200 Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 87 page  2018-2021 Microchip Technology Inc. DS00003093C Draft-page 57 ECE1200 6.11.10 ERROR CYCLE ADDRESS 0 REGISTER 6.11.11 ERROR CYCLE ADDRESS 1 REGISTER 6.11.12 ERROR CYCLE ADDRESS 2 REGISTER 6.11.13 ERROR CYCLE ADDRESS 3 REGISTER 6.11.14 ERROR CYCLE ATTRIBUTES REGISTER Index F4h of Logical Device 01h Bits Description Type Default Reset Event 7:0 Byte 0 of the LPC address that was being presented on the occurrence of the last error. This is the least-significant byte of any address. R/W 00h eSPI_RESET Index F5h of Logical Device 01h Bits Description Type Default Reset Event 7:0 Byte 1 of the LPC address that was being presented on the occurrence of the last error. In I/O accesses, this is the most-significant address byte. R/W 00h eSPI_RESET Index F6h of Logical Device 01h Bits Description Type Default Reset Event 7:0 Byte 2 of the LPC address that was being presented on the occurrence of the last error. Valid in Memory accesses only. R/W 00h eSPI_RESET Index F7h of Logical Device 01h Bits Description Type Default Reset Event 7:0 Byte 3 of the LPC address that was being presented on the occurrence of the last error. Valid in Memory accesses only, as the most-significant address byte. R/W 00h eSPI_RESET Index F8h of Logical Device 01h Bits Description Type Default Reset Event 7:2 Reserved R 00h - 1 RD_NWR ‘1’ = The last LPC error occurred on a Read access. ‘0’ = The last LPC error occurred on a Write access. R/W 0 eSPI_RESET 0IO_NMEM ‘1’ = The last LPC error occurred on an I/O access, and the low-order two bytes of the Error Cycle Address registers hold the I/O space address. ‘0’ = The last LPC error occurred on a Memory access, and all four bytes of the Error Cycle Address registers are used to hold the Memory address. R/W 0 eSPI_RESET |
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