ECE1200 datasheet(9/87 Pages) MICROCHIP

9 / 87 page

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DS00003093C Draft-page 9

ECE1200

4: In this configuration, the ECE1200 presents the output HOST_RST_ACK to indicate that its LPC bus has

become idle after the last transfer from the Host CPU, before an LRESET# event. This may optionally be

used

the

Primary

eSPI

Slave

device

delay

its

Virtual

Wire

handshake

HOST_RST_WARN/HOST_RST_ACK with the Host Chipset.

This signal is not a requirement, but may assist in this eSPI-specific handshake feature if desired. Although

the ECE1200 receives the HOST_RST_WARN Virtual Wire, it does not have direct authority to send the

HOST_RST_ACK handshake response itself, and is required to go through the Primary Slave instead.

Without this connection, there is no concern in legacy LPC systems. Historically, the LPC bus does not need

to be idle before it gets reset. Neither the ECE1200 nor its downstream devices will be disrupted without it.

5: The SUSWARN# and SUSACK# signals are shown connected together. This is not strictly required in this

configuration, but is harmless and inexpensive, and is recommended for uniformity since all other configu-

rations do require some connection. If this cannot be done, then tie the SUSACK# pin to a valid digital state,

low or high. SUSWARN# is an output, and may be left unconnected.

ECE1200 Datasheet(PDF) 9 Page - Microchip Technology