ECE1200 datasheet(38/87 Pages) MICROCHIP

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ECE1200

DS00003093C Draft-page 38

 2018-2021 Microchip Technology Inc.

The slots INTA# through INTD# are disabled by default, but may be assigned an IRQ number over eSPI using registers

in Logical Device 00h, at indexes B8h through BBh. Levels on these slots are simply propagated to the PCH on the

designated eSPI IRQ Virtual Wires, and the processing of them is left to the APIC block of the PCH and the ISRs

attached to them.

The SMI# and IOCHK# slots are optional and disabled by default, but may be enabled as desired.

• SMI# will be transmitted over eSPI always as the SMI# Virtual Wire. Use SERIRQ Exception Enables Register in

Logical Device 01h to enable the Serial IRQ slot.

• The IOCHK# slot can be attached to any one of four Virtual Wires for error handling. Use SERIRQ Exception

Enables Register in Logical Device 01h to enable the slot, and Global registers IOCHK Non-Posted Error Han-

dling Register, IOCHK Posted Error Handling Register and IOCHK Idle Error Handling Register to configure the

handling for IOCHK# occurring within a Non-Posted transfer, a Posted transfer, or neither (LPC idle), respectively.

6.8.5

SELECT LPC CLOCK OUTPUTS

By default, both LPC Clock outputs are running. To save power, it is possible to turn off an Enable bit provided for each

output. A disabled clock is unaffected by the CLKRUN# feature, and remains held low. See the Clock Enable Register

in the Logical Device 01h register space.

6.8.6

SET UP OPTIONAL CLKRUN# CLOCK GATING

By default, any LPC Clock pin that remains enabled (above) is free-running. To optionally allow the CLKRUN# function

to gate them during idle LPC and SERIRQ times, it is necessary to:

Designate whether each pin will be controlled by CLKRUN#, using bits in the Clock Enable Register in the Logical

Device 01h register space.

Enable the CLKRUN# feature itself in the CLKRUN Control Register in the Logical Device 01h register space.

Until this is done, the CLKRUN# pin is held low, and the designated LPC clock output(s) will not be gated.

For CLKRUN# gating to operate, it is also necessary for the Serial IRQ feature to be set to Quiet Mode. Until this is

done, the CLKRUN# pin will remain low and clocks will not be gated.

6.8.7

SET UP OPTIONAL LPC ERROR HANDLING

The various errors that may be signaled in LPC traffic may be routed over eSPI. These are “Unclaimed” (which includes

invalid SYNC codes) and “SYNC Abort”, which is an error occurring in a Claimed cycle.

In eSPI terms, “Non-Posted” traffic (I/O Read or Write, and Memory Read) will unconditionally provide the eSPI UNSUC-

CESSFUL COMPLETION response on these errors, and this may be enough.

However, “Posted” traffic (Memory Write) does not have the opportunity to respond this way. If error indications are

required, this must be done asynchronously using a Virtual Wire.

Therefore, an LPC error condition may be attached to a Virtual Wire for reporting of Posted errors. Non-Posted errors

may also be attached to Virtual Wires in addition to the UNSUCCESSFUL COMPLETION response. The Virtual Wire

may be selected as either ERROR_FATAL, ERROR_NONFATAL, SMI# or SCI#.

See the Global register set, indexes 08h through 10h for these settings. By default, no Virtual Wire handlings are

selected.

Errors are reported in the Global registers at indexes 12h and 13h. These registers are where polling for errors occurs

and where they can be acknowledged / cleared.

In addition, there is a group of logging registers in Logical Device 01h, indexes F2h through F8h, where the LPC error

type, the LPC address and the access type (Read vs.Write, and I/O vs. Memory) are captured. These registers are not

cleared on PLTRST events, so they may be read after a system restart.

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