ECE1200 datasheet(37/87 Pages) MICROCHIP

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DS00003093C Draft-page 37

ECE1200

Re-assignment of this default Base Address is only required if the system’s Port 80h display function is not located on

the LPC bus, downstream of the ECE1200. See Section 6.8.2.1, "Routing Within the Host Chipset," on page 37, for a

brief application note on possible system routing variations.

If it is desired to perform a Base Address re-assignment, use the following steps:

According to Section 6.8.2.1, "Routing Within the Host Chipset," on page 37, set up the Host Chipset to ensure

that Port 80h / RPR traffic is routed to the ECE1200, if only temporarily.

According to Section 6.3.1, write the value 55h to the INDEX I/O location at 8Ch to enable register access.

If it is possible that this sequence is happening without a previous PLTRST# reset assertion, ensure that Logical

Device 0 is selected, by doing the following:

a) Write 07h to the INDEX location 8Ch, designating the global Logical Device Number Register.

b) Write 00h to the DATA location 8Dh.

Designate a new Base Address:

a) Write 36h to the INDEX location 8Ch, designating the I/O BAR Address LS Register.

b) Write the LS byte of the new Base Address to the DATA location 8Dh.

Write 37h to the INDEX location 8Ch, designating the I/O BAR Address MS Register.

d) Write the MS byte of the new Base Address to the DATA location 8Dh.

Note that all four Writes must be performed, and in this order, even if they do not change a value that is already

in one of the registers. Until this sequence is done completely, none of the 16-bit value changes internally.

If routing in the Chipset for Step 1 above was intended to be temporary, it may now be restored.

From this point onward, the ECE1200 will recognize only the new Base Address, and no longer 8Ch/8Dh, for accesses

to its internal registers.

6.8.2.1

Routing Within the Host Chipset

The initial default routing within the Host Chipset directs the Port 80h I/O region (including Ports 8Ch/8Dh) to the eSPI

bus, on eSPI Chip Select #0 (CS0#).

In eSPI Chipsets supporting more than one device on separate Chip Selects, the ECE1200 may reside on a different

Chip Select (for example CS1#). A bit is provided in these Chipsets to re-route the Port 80h / RPR region to one of these

other Chip Selects. As an example, for eSPI CS1# in the C620 series Chipset’s PCH, this is the DPCS1RE bit, at bit

position [14] of register PCCS1IORE.

Another available routing selection in most Chipsets is to map the Port 80h / RPR region onto the PCIe bus instead of

eSPI. Since that routes the region away from eSPI entirely, the ECE1200 will need to have its Base Address re-assigned

elsewhere unconditionally. Within the PCH, this routing is controlled by the RPR bit in register GCR, but note that this

bit’s default state still routes to eSPI initially.

6.8.3

ENABLE REGISTER ACCESS

If not already done as part of Section 6.8.2, "Base Address Re-Assignment (Optional)," on page 36, then write the value

55h to the INDEX I/O location to enable register access according to Section 6.3.1.

6.8.4

SET UP SERIAL IRQ

The SERIRQ Enable and Mode Register must be initialized in order to set up and start Serial IRQ traffic. It is in the

Logical Device 01h register region.

When starting the Serial IRQ function, it is necessary to set the SIRQ_EN bit and the SIRQ_MD bit both to ‘1’ in the

same Write transfer. This starts the Serial IRQ traffic in Continuous Mode initially. Quiet Mode may be selected optionally

at a later time.

IRQ slots are propagated over eSPI using their legacy IRQ numbers by default, but may be re-designated if desired

using registers in Logical Device 00h, at indexes ACh through B7h.

ECE1200 Datasheet(PDF) 37 Page - Microchip Technology

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