ECE1200 datasheet(70/87 Pages) MICROCHIP

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ECE1200

DS00003093C Draft-page 70

 2018-2021 Microchip Technology Inc.

9.5

Voltage Sequencing and Power Good Timing

9.5.1

VTR SEQUENCING AND RESETI# TIMING

9.6

Strap Option Sampling Timing

The ESPI_STRAP_0 and ESPI_STRAP_1 pins are sampled and latched internally for test purposes. It is recommended

that they be left floating or N/C except in XNOR Chain test mode, so that internal weak pull-ups can pull them high to

the VTR_33 level.

9.7

System Power State Transition Diagrams

The following set of diagrams illustrates the behavior of the ECE1200 during transitions in the system-level power state.

TABLE 9-6:

VTR TIMING

Parameters

Symbol

MIN

TYP

MAX

Unit

Notes

VTR_33 > 1.8V to VTR_18 or

VTR_CORE_18 On

VTR_18 and VTR_CORE_18 Off to VTR_33

< 1.8V

All VTR voltages valid to RESETI# high

Note:

RESETI# low to any VTR voltage invalid

Note:

RESETI# must remain low and must not glitch during VTR power presentation / removal.

TABLE 9-7:

GENERIC STRAP OPTION SAMPLING TIMING

Parameters

Symbol

MIN

TYP

MAX

Units

Notes

ESPI_STRAP_[1:0] pins setup to

RESETI# Rising Edge

tSTRAPSET

500

ESPI_STRAP_[1:0] pins hold from

RESETI# Rising Edge

tSTRAPHOLD

0us

VTR_33

VTR_CORE_18

VTR_18

1.8V

3.3V

1.8V

RESETI#

3.3V

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