ZL30263 datasheet(18/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

and S is the peak-to-peak spread percentage expressed as a decimal (example ±0.5% → S=0.01)

For down-spread applications (ASCR.DWNEN=1), such as PCI Express Refclk, the frequency modulation is triangle-

wave down-spread of up to -1% deviation from the nominal frequency with modulation rate configurable from 25kHz

to 55kHz. The spread deviation and modulation rate are controlled by specifying an increment/decrement step in the

AID registers and the number of APLL input clock cycles to increment and decrement in the ASCNT registers. The

values to be written to the device are calculated as follows:

�� = �� (

��

2 ∗ ��

) − 2

�� = �� (

��

∗

�� ∗ 233

�� + 2

)

All of the input parameters are the same as for center spread above. Note the small differences between these down-

spread equations and the center-spread equations above. ASCNT here has 2 in the denominator while it has 4 for

center-spread. AID has 233 in the numerator for down-spread while it has 232 for center-spread.

During spread-

spectrum operation using the APLL’s feedback divider, AFBREM should be set to 0, AFBDEN should

be set to 1 and AFBBP should be set to 0. Spread-spectrum modulation only occurs when the APLL is locked

(APLLSR.ALK=1).

5.5.8.2 Using the Fractional Output Divider

When ACR1.USEFDIV=1 the device performs frequency modulation by modulating the fractional output divider value

starting from the nominal value specified in the FDIV registers.

For center-spread applications (ASCR.DWNEN=0), the frequency modulation is triangle-wave center-spread of up

to ±5% deviation from the center frequency with modulation rate configurable from 10kHz to 100kHz. (Values outside

of these ranges are often achievable as well.) The spread deviation and modulation rate are controlled by specifying

an increment/decrement step in the AID registers and the number of APLL input clock cycles to increment and

decrement in the ASCNT registers. The ASCR.CNTEN register field must also be set propertly. The values to be

written to the device are calculated as follows:

CNTEN = 0 for FIN < 50MHz

1 for 50MHz  FIN < 100MHz

2 for FIN ≥ 100MHz

�� = �� (

��

4 ∗ �� ∗ 2��

) − 2

�� = �� (

��

∗

�� ∗ 234

(�� + 2) ∗ (1 − 0.5��)

)

where FVCO

is the APLL”s VCO frequency in Hz,

FIN

is the input frequency at the APLL’s PFD in Hz,

FOUT

is the fractional output divider block’s output frequency in Hz,

FMOD is the spread-spectrum modulation frequency in Hz,

and S is the peak-to-peak spread percentage expressed as a decimal (example ±0.5% → S=0.01)

For down-spread applications (ASCR.DWNEN=1), such as PCI Express Refclk, the frequency modulation is triangle-

wave down-spread of up to -10% deviation from the nominal frequency with modulation rate configurable from 10kHz

to 100kHz. (Values outside of these ranges are often achievable as well.) The spread deviation and modulation rate

are controlled by specifying an increment/decrement step in the AID registers and the number of APLL input clock

cycles to increment and decrement in the ASCNT registers. The ASCR.CNTEN register field must also be set

propertly. The values to be written to the device are calculated as follows:

CNTEN = 0 for FIN < 50MHz

1 for 50MHz  FIN < 100MHz

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