ZL30263 datasheet(77/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

Characteristics

Symbol

Min.

Typ.1

Max

Units

Notes

VDDL supply current change from enabling or

disabling an output for CMOS or HSTL

IDDLC

VDDOx supply current change from enabling or

disabling an LVDS output

IDDOD

VDDOx supply current change from enabling or

disabling an LVPECL output

IDDOP

VDDOx supply current change from enabling or

disabling an HCSL output

IDDOHC

Note 5

VDDOx supply current change from enabling or

disabling a CMOS output

IDDOC

Note 3

VDDOx supply current change from enabling or

disabling an HSTL output

IDDOHS

Note 4

Note 1:

Typical values measured at nominal supply voltages and 25

C ambient temperature.

Note 2:

Max IDD measurements made with all blocks enabled, 650MHz signals on IC1 and IC2 inputs, 187.5MHz signal on IC3, Crystal driver

and doubler off , VCO frequency of 3750MHz, APLL output dividers dividing by 6, all MSDIV dividing by 2, all LSDIV dividing by 2,

all outputs enabled as LVPECL outputs driving 156.25MHz signals, and all VDDO at same voltage as VDDH. Typical IDD

measurements made with same setup as max IDD but APLL fractional dividers disabled and only six outputs enabled with LVDS

signal format.

Note 3:

VDDOx=3.3V, 1x drive strength, fO=250MHz, 2pF load

Note 4:

VDDOx=1.8V, 2x drive strength, fO=100MHz, 100 differential termination.

Note 5:

 to ground each on OCxP and OCxN.

Table 7 - Electrical Characteristics: Non-Clock CMOS Pins

Characteristics

Symbol

Min.

Typ.

Max.

Units

Notes

Input high voltage

0.7 x

VDDIO

Input low voltage

0.3 x

VDDIO

Input leakage current, all digital inputs

-10

A

Note 1

Input capacitance

Input capacitance, SCL/SCLK, SDA/MOSI

Input hysteresis, SCL and SDA in I2C Bus Mode

0.05 x

VDDIO

Output leakage (when high impedance)

-10

A

Note 1

Output high voltage

0.8 x

VDDIO

IO = -3.0mA

Output low voltage

0.2 x

VDDIO

IO = 3.0mA

Clock output on GPIO pin, frequency

fOUT

MHz

Note 3

Clock output on GPIO pin,

rise/fall time

VDDIO=1.8V

tR, tF

2.3

Notes 3, 4

VDDIO=2.5V

1.5

Notes 3, 4

VDDIO=3.3V

1.2

Notes 3, 4

Note 1:

0V < VIN < VDDIO for all other non-clock inputs.

Note 2:

VOH does not apply for SCL and SDA in I

2C interface mode since they are open drain.

Note 3:

To output a clock on a GPIO pin, an OCx output must be configured with NEGLSD=1 and SRLSEN=1 in OCxCR3 and the GPIO

must be configured to as a status output following OCxSR.LSCLK (see the GPIOCR and GPIOxSS registers). Output jitter is not

guaranteed for clock signals on GPIO pins but is typically 1 to 5ps rms 12kHz to 20MHz.

Note 4:

20%-80%, 15pF load.

ZL30263 Datasheet(PDF) 77 Page - Microchip Technology

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