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ZL30263 Datasheet(PDF) 86 Page - Microchip Technology |
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ZL30263 Datasheet(HTML) 86 Page - Microchip Technology |
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86 / 94 page ![]() ZL30260-ZL30263 Data Sheet 86 © 2021 Microchip Technology Inc. DS20006554A Table 21 - Electrical Characteristics: SPI Master Interface Timing (ZL30260 and ZL30262 Only) VDDIO = 3.3V±5% or 2.5V±5% or 1.8V±5% Characteristics (Notes 1 to 3) Symbol Min. Typ. Max. Units Notes SCLK output frequency fBUS 5 MHz SCLK output cycle time tCYC 200 ns SCLK output duty cycle tCLKH/ tCYC 45 50 55 % CSN output setup to first SCLK rising edge tSUC 200 ns CSN output hold after last SCLK falling edge tHDC 200 ns CSN output high time tCSH 200 ns MISO input setup time to SCLK rising edge tSU 15 ns MISO input hold time from SCLK rising edge tHD 5 ns MOSI output valid from SCLK falling edge tDV 10 ns SCLK, CSN, MOSI output rise time, fall time tR, tF 15 ns MISO input rise time, fall time tR, tF 10 ns Note 1: All timing is specified with 100pF load on all SPI pins. Note 2: All parameters in this table are guaranteed by design or characterization. Note 3: See timing diagram in Figure 19. Figure 19 - SPI Master Interface Timing CSN SCLK tSUC tCYC tCLKL tCLKH tSU tHD MOSI MISO tHDC tCSH tDV |
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