ZL30263 datasheet(22/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

When MSDIV=0, OCxSTOP.MODE=11 (stop high then go high-impedance) can be used to make outputs high-

impedance, but the

action won’t necessarily be glitchless. To use this behavior to get “stop low then go-impedance”

behavior, OCxCR2.POL can be set to 1.

Note that when OCxCR3.NEGLSD=1 the start-stop logic is bypassed for the OCxN pin, and OCxN may not start/stop

without glitches.

Each output has a status register (OCxSR) with several stop/start status bits. The STOPD bit is a real-time status bit

indicating stopped or not stopped. The STOPL bit is a latched status bit that is set when the output clock has stopped.

The STARTL bit is a latched status bit that is set when the output clock has started.

5.7

Microprocessor Interface

The device can communicate over a SPI interface or an I2C interface.

In SPI mode ZL3026x devices without internal EEPROM can be configured at reset to be a SPI slave to a processor

master or a SPI master to an external EEPROM slave. (SPI master operation changes to SPI slave operation after

auto-configuration from the external EEPROM is complete.) The ZL3026x devices with internal EEPROM can only

be configured as a SPI slave to a processor master. All devices are always slaves on the I2C bus.

Section 5.2 describes reset pin settings required to configure the device for these interfaces.

5.7.1

SPI Slave

The device can present a SPI slave port on the CSN, SCLK, MOSI, and MISO pins. SPI is a widely used master/slave

bus protocol that allows a master and one or more slaves to communicate over a serial bus. SPI masters are typically

microprocessors, ASICs or FPGAs. Data transfers are always initiated by the master, which also generates the SCLK

signal. The device receives serial data on the MOSI (Master Out Slave In) pin and transmits serial data on the MISO

(Master In Slave Out) pin. MISO is high impedance except when the device is transmitting data to the bus master.

Bit Order. The register address and all data bytes are transmitted most significant bit first on both MOSI and MISO.

Clock Polarity and Phase. The device latches data on MOSI on the rising edge of SCLK and updates data on

MISO on the falling edge of SCLK. SCLK does not have to toggle between accesses, i.e., when CSN is high.

Device Selection. Each SPI device has its own chip-select line. To select the device, the bus master drives its CSN

pin low.

Command and Address. After driving CSN low, the bus master transmits an 8-bit command followed by a 16-bit

Table 3 - SPI Commands

Command

Hex

Bit Order, Left to Right

Write Enable

0x06

0000 0110

Write

0x02

0000 0010

Read

0x03

0000 0011

Read Status

0x05

0000 0101

Read Transactions. The device registers are accessible when EESEL=0. On ZL3026x devices with internal

EEPROM, the EEPROM memory is accessible when the EESEL bit is 1. On ZL3026x devices without internal

EEROM, the EESEL bit must be set to 0. After driving CSN low, the bus master transmits the read command followed

by the 16-bit address. The device then responds with the requested data byte on MISO, increments its address

counter, and prefetches the next data byte. If the bus master continues to demand data, the device continues to

provide the data on MISO, increment its address counter, and prefetch the following byte. The read transaction is

completed when the bus master drives CSN high. See Figure 6.

master transmits the write command followed by the 16-bit register address followed by the first data byte to be

written. The device receives the first data byte on MOSI, writes it to the specified register, increments its internal

address register, and prepares to receive the next data byte. If the master continues to transmit, the device continues

to write the data received and increment its address counter. The write transaction is completed when the bus master

drives CSN high. See Figure 8.

ZL30263 Datasheet(PDF) 22 Page - Microchip Technology

ZL30263 Datasheet(HTML) 22 Page - Microchip Technology

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