ZL30263 datasheet(70/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

OCxCR3

Output Clock x Configuration Register 3

OC1: 204h, OC2: 214h, OC3: 224h, OC4: 234h, OC5: 244h

OC6: 254h, OC7: 264h, OC8: 274h, OC9: 284h, OC10: 294h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

SRLSEN

—

NEGLSD

LSSEL

—

ASQUEL

—

LSDIV[24]

Default

Bit 7: Enable LSDIV Statuses (SRLSEN). This bit enables the OCxSR.LSCLK real-time status bit and its associated

latched status bit OCxSR.LSCLKL.

0 = LSCLK status bit is not enabled (low)

1 = LSCLK status bit is enabled

Bit 5: OCxN Low Speed Divider (NEGLSD). This bit selects the source of the clock on the OCxN pin in CMOS

mode. See section 5.6.2.

0 = Same as OCxP

1 = Output of the LSDIV divider

Note: NEGLSD should only be set to one in two-CMOS mode (OCxCR2.OCSF=100 or 111), when

OCxCR2.POL=0, and when OCxCR3.LSSEL=0.

Bit 4: LSDIV Select (LSSEL). This bit selects the source of the output clock. When the MSDIV divider is selected

(LSSEL=0) the LSDIV divider output can be independently selected as the source for the OCxN pin (in CMOS output

mode) or monitored by the OCxSR.LSCLK status bit. This bit is only valid when OCxCR1.MSDIV > 0. See section

5.6.2.

0 = The output clock is sourced from the MSDIV divider.

1 = The output clock is sourced from the LSDIV divider.

Bit 2: Auto-Squelch Enable (ASQUEL). This bit enables automatic squelching of the output clock whenever (a)

automatic input switching is enabled for the APLL, and (b) the input monitors indicate that the inputs specified by the

APLL’s APLLMUX and ALTMUX fields are both invalid. OCxSTOP.MODE specifies the type of stop (high, low, high-

impedance) and the output clock edge on which to stop. When a differential output or a CMOS complementary output

is squelched, its OCxN pin is opposite polarity of its OCxP pin.

0 = Auto-squelch disabled

1 = Auto-squelch enabled

Bit 0: Low-Speed Divider Value (LSDIV[24]). See the OCxDIV1 register description.

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