ZL30263 datasheet(81/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

Figure 17 - Example External Components for Output Signals

Figure 17 part c) covers the case where an existing receiver has AC coupling caps followed by an internal or external 100

 termination resistor.

The driver requires a DC path between its POS and NEG pins even in this case. A 200

 resistor is recommended. Since this arrangement

attenuates the signal by one third, The OCxDIFF.VOD field should be set 50% higher to compensate.

Table 14 - Electrical Characteristics: APLL Frequencies

Characteristics

Symbol

Min.

Typ.

Max.

Units

Notes

APLL VCO frequency range

fVCO

3715

4180

MHz

APLL PFD input frequency

tPFD

9.72

156.25

MHz

Table 15 - Electrical Characteristics: Jitter and Skew Specifications

Characteristics

Test Conditions

Min

Typ

Max

Units

APLL Jitter Transfer Bandwidth

600

kHz

Output to Output Skew

Note 4

100

Input-to-Output Delay Variation, APLL external

feedback, OC1 internal path

Note 12

110

160

APLL, Integer Output Divider

Phase Jitter, 156.25MHz

Notes 1, 3

0.23

0.275

ps RMS

Notes 2, 3

0.155

0.175

ps RMS

PCI Express 1.1, Common Refclk Jitter

Total Jitter, Notes 6, 11

ps pk-pk

PCI Express 2.1, Common Refclk Jitter

10kHz to 1.5MHz, Note 6

0.1

0.3

ps RMS

1.5MHz to 50MHz, Note 6

1.6

2.1

ps RMS

PCI Express 3.0, Common Refclk Jitter

Note 6

0.08

0.10

ps RMS

PCI Express 4.0, Common Refclk Jitter

Note 6

0.08

0.10

ps RMS

PCI Express 5.0, Common Refclk Jitter

Note 6, 13

0.068

0.077

ps RMS

APLL, Fractional Output Divider

Phase Jitter, 156.25MHz

Integer divisor, Notes 1, 8

0.26

0.3

ps RMS

Frac. divisor, Note 1, 8

0.35

0.425

ps RMS

PCI Express 1.1, Common Refclk Jitter

Total Jitter, Notes 9, 11

ps pk-pk

Differential

Receiver

100



LVDS,

LVPECL,

or generic

diff erential

receiver with

1-2. 1V Vcm





HCSL

Receiver





100



CML

Receiver



Microsemi

Prog. Di ff

mode

LVDS or Prog.

Diff mode

HCSL mode

CMOS

Receiver



source-series termination

Microsemi

CMO S mode

100



Microsemi

Prog. Di ff

mode

Internal or external

termination on receiver

side of AC-coupling caps.

200



Driver requires DC pat h between + and

– pins. 200

 recommended.



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