ZL30263 datasheet(50/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

OCxSR

Output Clock x Status Register

OC1: 50h, OC2: 51h, OC3: 52h, OC4: 53h, OC5: 54h

OC6: 55h, OC7: 56h, OC8: 57h, OC9: 58h, OC10: 59h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

LSCLKIE

LSCLKL

LSCLK

STARTIE

STARTL

STOPIE

STOPL

STOPD

Default

Bit 7: (LSCLKIE). This bit enables the LSCLKL latched status bit to

send an interrupt request into device’s interrupt

logic.

0 = Interrupt is disabled

1 = Interrupt is enabled

Bit 6: (LSCLKL). This latched status bit is set when the low-speed divider output clock transitions low-to-high.

Writing a 1 to this bit clears it.

0 = Low speed output clock has not transitioned low to high

1 = Low speed output clock has transitioned low to high

Bit 5:

(LSCLK). This real-time status bit follows the level of the low-speed divider output clock when the

OCxCR3.SRLSEN bit is set.

0 = LSCLK is high

1 = LSCLK is low

Bit 4: (STARTIE). This bit enables the STARTL latched status bit to

send an interrupt request into device’s interrupt

logic.

0 = Interrupt is disabled

1 = Interrupt is enabled

Bit 3: (STARTL). This latched status bit is set when the output clock signal has been started after being stopped.

Writing a 1 to this bit clears it. See section 5.6.6.

0 = Output clock signal has not resumed from being stopped

1 = Output clock signal has resumed from being stopped

Bit 2: (STOPIE). This bit enables the STOPL latched status bit to

send an interrupt request into device’s interrupt

logic.

0 = Interrupt is disabled

1 = Interrupt is enabled

Bit 1: (STOPL). This latched status bit is set when the output clock signal has been stopped. Writing a 1 to this bit

clears it. See section 5.6.6.

0 = Output clock signal has not stopped

1 = Output clock signal has stopped

Bit 0: (STOPD). This real-time status bit is high when the output clock signal is stopped and low when the output

clock is not stopped. See section 5.6.6.

0 = Output clock signal is not stopped

1 = Output clock signal is stopped

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