ZL30263 datasheet(19/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

2 for FIN ≥ 100MHz

�� = �� (

��

2 ∗ �� ∗ 2��

) − 2

�� = �� (

��

∗

�� ∗ 235

(�� + 2) ∗ (1 − 0.5��)

)

All of the input parameters are the same as for center spread above. Note the small differences between these down-

spread equations and the center-spread equations above. ASCNT here has 2 in the denominator while it has 4 for

center-spread. AID has 235 in the numerator for down-spread while it has 234 for center-spread.

During spread-spectrum operation using the fractional output divider, FREM should be set to 0, FDEN should be set

to 1 and FBP should be set to 0. The F1CR1.MODE field must be set to 1 when doing spread-spectrum modulation

with the fractional output divider value. Spread-spectrum modulation only occurs when the APLL is locked

(APLLSR.ALK=1).

5.5.9

APLL Phase Adjustment

The phase of the APLL’s output clock can be incremented or decremented. When the APLL’s AFBDIV value is not

an exact multiple of 0.5 then the phase adjustment step size is 1/8th of a VCO cycle. This phase step size is 30ps at

maximum VCO frequency of 4180MHz and 33.7ps at minimum VCO frequency of 3715MHz. The ACR4.PDSS field

specifies the phase decrement control signal, which can be the ACR4.DECPH bit or any of the four GPIOs. The

ACR4.PISS field specifies the phase increment control signal, which can be the ACR4.INCPH bit or any of the four

GPIOs. Phase is adjusted on every rising edge and every falling edge of the control signal. This phase adjustment

affects the output of the APLL’s output dividers (integer and fractional).

When the APLL’s AFBDIV value is an exact multiple of 0.5 then the phase adjustment step size is one VCO cycle.

5.6

Output Clock Configuration

The ZL30260 and ZL30261 have six output clock signal pairs while the ZL30262 and ZL30263 have ten. Each output

has individual divider, enable and signal format controls. In CMOS mode each signal pair can become two CMOS

outputs, allowing the device to have up to 12 or 20 output clock signals. Also in CMOS mode, the OCxN pin can have

an additional divider allowing the OCxN frequency to be an integer divisor of the OCxP frequency (example: OC3P

125MHz and OC3N 25MHz). The outputs can be aligned relative to each other, and the phases of output signals can

be adjusted dynamically with high resolution.

5.6.1

Output Enable, Signal Format, Voltage and Interfacing

To use an output, the output driver must be enabled by setting OCxCR2.OCSF

0, and the per-output dividers must

be enabled by setting the appropriate bit in the OCEN register. The per-output dividers include the medium-speed

divider, the low-speed divider and the associated phase adjustment/alignment circuitry and start/stop logic.

Using the OCxCR2.OCSF register field, each output pair can be disabled or configured as LVDS, LVPECL, HCSL,

HSTL, or one or two CMOS outputs. When an output is disabled it is high impedance, and the output driver is in a

low-power state. In CMOS mode, the OCxN pin can be disabled, in-phase or inverted vs. the OCxP pin. All of these

options are specified by OCxCR2.OCSF. The clock to the output driver can inverted by setting OCxCR2.POL=1. The

CMOS/HSTL output driver can be set to any of four drive strengths using OCxCR2.DRIVE.

When OCxCR2.OCSF=0001 the output driver is in LVDS mode. VOD is forced to 400mV and OCxDIFF.VOD is

ignored. VCM can be configured in OCxDIFF.VCM, but the default value of 0000 is typically used to get VCM=1.23V

for LVDS.

When OCxCR2.OCSF=0010 the output driver is in programmable differential mode. In this mode the output swing

(VOD) can be set in OCxDIFF.VOD and the common-mode voltage can be set in OCxDIFF.VCM. Together these

fields allow the output signal to be customized to meet the requirements of the clock receiver and minimize the need

for external components. By default, when OCSF=0010 the output is configured for LVPECL signal swing with a

1.23V common mode voltage. This gives a signal that can be AC-coupled (after a 100

 termination resistor) to

receivers that are LVPECL or that require a larger signal swing than LVDS. The output driver can also be configured

for LVPECL output with standard 2.0V common-mode voltage by seting OCxDIFF.VCM for 2.0V and setting

OCxREG.VREG appropriately.

ZL30263 Datasheet(PDF) 19 Page - Microchip Technology

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