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ZL30263 Datasheet(PDF) 63 Page - Microchip Technology |
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ZL30263 Datasheet(HTML) 63 Page - Microchip Technology |
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63 / 94 page ![]() ZL30260-ZL30263 Data Sheet 63 © 2021 Microchip Technology Inc. DS20006554A Register Name: F1DEN1 Register Description: APLL Fractional Output Divider Denominator Register 1 Register Address: 146h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name FDEN[7:0] Default 0 0 0 0 0 0 0 1 Bits 7 to 0: Fractional Output Divider Denominator (FDEN[7:0]). The full 32-bit FDEN[31:0] field spans F1DEN1 through F1DEN4 registers. FDEN is an unsigned integer that specifies the denominator of the fractional output divider value. The value FDEN=0 is undefined. See section 5.5.5. Register Name: F1DEN2 Register Description: APLL Fractional Output Divider Denominator Register 2 Register Address: 147h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name FDEN[15:8] Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Fractional Output Divider Denominator (FDEN [15:8]). See the F1DEN1 register description. Register Name: F1DEN3 Register Description: APLL Fractional Output Divider Denominator Register 3 Register Address: 148h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name FDEN[23:16] Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Fractional Output Divider Denominator (FDEN [23:16]). See the F1DEN1 register description. Register Name: F1DEN4 Register Description: APLL Fractional Output Divider Denominator Register 4 Register Address: 149h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name FDEN[31:24] Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Fractional Output Divider Denominator (FDEN [31:24]). See the F1DEN1 register description. |
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