ZL30263 datasheet(91/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

11. Data Sheet Revision History

Revision

Description

26-Sep-2016

First general release

08-Dec-2016

On page 1 added PCIe bullet.

In Table 1, OCx pin description, clarified what is programmable for each mode.

Added new Figure 17.

In Table 15 added max Input-to-Output Delay Variation numbers for external feedback using

on-die path.

In Table 17 added min, typ and max values for buffer Input-to-Output Propagation Delay. In

footnotes 3 and 4 added “Measured at 125MHz”.

In Figure 17 added CMOS diagram.

12-Jun-2017

In section 2.4 and section 5.5.6.2 added note that NCO resolution of 1ppt is possible.

Corrected references to MCR1.XAB to MCR2.XAB.

Corrected four occurrences of VCCOx to VDDOx.

Added pullup recommendations to SCL/SCLK and SDA/MOSI pin descriptions.

Change ID2

.REV default value to “contact factory”.

In OCxCR2

.OCSF HCSL decode, deleted “VCM and VOD are ignored”.

17-Jul-2017

In Figure 17 removed the 50ohm to ground termination option from the CMOS diagram.

05-Sep-2017

In Table 1

TEST/GPIO3 pin description, changed “TEST must be low on the rising edge of

RSTN” to “Typically TEST should be low on the rising edge of RSTN, but see section 5.2 for

some options.”

In section 5.6.2 added the statement that maximum input frequency to the medium-speed

divider is 750MHz.

In section 5.6.5 clarified that signals from the same IntDiv or FracDiv are aligned and that

aligning clocks from IntDiv with clocks from FracDiv is not supported.

In section 5.9 added new subsection 5.9.1 to guide users in the use of external RC reset

circuits.

19-Jan-2018

In the F1REM1 regi

ster description deleted “The value FREM=0 is undefined. When FBP=0,

FREM must be set to 0.

”

In the F1DEN1

In the F1BP register description

deleted “When FBP=0, FREM must be set to 0 and FDEN

must be set to 1.

”

In the AFBREM1 registe

r description deleted “When AFBBP=0, AFBREM must be set to 0.”

IIn the AFBBP

AFBDEN must be set to 1.

”

29-May-2018

On page 1 and in section 2.3 changed wording to indicate PCIe 1-4 compliance.

In OCxCR3.NEGLSD description added to note that OCxCR3.LSSEL must be 0 to set

NEGLSD=1.

14-Sep-2018

In Table 17, corrected typo for "Input-to-Output Propagation Delay, from IC3 input" in the Note

4 row where the max of 2.8 was less than typical of 3.4. Corrected the max to 3.8.

In the OCxCR2.OCSF description, deleted "(must have VDDOx=VDDH=3.3V)" from the HCSL

decode.

Updated Table 10 Note 1 and Table 11 Note 1 and added cross reference to Figure 17 parts a)

and b).

Updated Figure 17 to include new part c) and added noted about part c) below the figure.

In section 5.9.1 second paragraph added need for current-limiting series resistor between

source of reset signal and device RSTN pin.

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