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ZL30263 Datasheet(PDF) 29 Page - Microchip Technology |
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ZL30263 Datasheet(HTML) 29 Page - Microchip Technology |
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29 / 94 page ![]() ZL30260-ZL30263 Data Sheet 29 © 2021 Microchip Technology Inc. DS20006554A For ZL30260 and ZL30262, the device optionally can configure itself at reset from an external EEPROM connected to its SPI interface. The EEPROM can store up to eight configurations, known as configurations 0 through 7. As described in section 5.2.1, IF[1:0] must be 11 at reset, and the device configuration to be used is specified by the values of the AC[2:0] pins at reset (0 through 7). For ZL30261 and ZL30263, the internal EEPROM memory can store up to eight device configurations, known as configurations 0 through 7. As described in section 5.2.2, the device configuration to be used is specified by the values of the AC[2:0] pins at reset. 5.11.1 Generating Device Configurations Device configurations are most easily generated using the evaluation software. This is true for auto-configurations stored in internal or external EEPROM and for configurations that are written to the device by a system processor. See section 5.12 for guidance if device configurations must be developed without using the evaluation software. 5.11.2 Direct EEPROM Write Mode (ZL30261 and ZL30263 Only) To simplify writing the device’s internal EEPROM during manufacturing, the device has a test mode known as direct EEPROM write mode. The device enters this mode when TEST=1, AC[2:0]=000 and IF[1:0]=11 on the rising edge of RSTN. In this mode the EEPROM memory is mapped into the address map and can be written as needed to store configuration scripts in the device. Device registers are not accessible in this mode. The device exits this mode on the rising edge of RSTN. Note: the device drives the MISO pin continually during this mode. Therefore this mode cannot be used when MOSI and MISO are tied together as described in the Design Option: Wiring MOSI and MISO Together paragraph in section 5.7.1. 5.11.3 Holding Other Devices in Reset During Auto-Configuration Using the appropriate GPIOCR and GPIO0SS registers, a GPIO pin can be configured to follow the GLOBISR.BCDONE status bit. This GPIO can then be used as a reset signal to hold other devices (device that use clocks from this device) in reset while the device configures itself. As an example, to configure GPIO0 to follow BCDONE with 0=reset add the following writes at the beginning of the configuration file: write 0x1F to GPIO0SS and write 0x04 to GPIOCR1. 5.12 Configuration Sequence Device configurations are most easily generated using the evaluation software, which automatically generates configurations that follow Microchip ’s suggested sequence. To develop device configurations manually (i.e. from device documentation rather than the evaluation software) see Application Note ZLAN-590 for Microchip ’s suggested device configuration sequence. 5.13 Power Supply Decoupling and Layout Recommendations Application Note ZLAN-592 describes recommended power supply decoupling and layout practices. 5.14 Choosing Among Core Power Supply Options The device supports the following core supply voltage options: VDDH VDDL 3.3V 3.3V 3.3V 1.8V 2.5V 2.5V 2.5V 1.8V Choosing the best option depends on several factors including supply voltages available on the board, willingness to use low-dropout (LDO) linear regulators to make local power supplies for the device, board power supply noise and mitigation strategies, target jitter performance, and how many device resources are enabled. Starting with the VDDH=VDDL=3.3V option, the advantages of this option are (1) the device only requires a single power supply voltage (assuming all output driver VDDOx supplies are also 3.3V), and (2) internal regulation is used for the APLL, maximizing power supply noise rejection. The disadvantage is that power consumption is higher than other options. |
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