ZL30263 datasheet(30/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

The VDDH=3.3V, VDDL=1.8V option does require two core power supply voltages, but internal regulation is used for

the APLL, maximizing power supply noise rejection. Also this option does not have either of the two disadvantages

of the VDDH=VDDL=3.3V option. If the application can provide 3.3V and 1.8V supplies to the device, this option is

highly recommended as a good balance of lower power consumption and better power supply noise rejection.

The VDDH=VDDL=2.5 option is for applications that do not have a 3.3V power supply and do not want to provide an

LDO to make a 3.3V supply. The advantages of this option are (1) the device only requires a single power supply

voltage (assuming all output driver VDDOx supplies are also 2.5V), and (2) lower power consumption than the

VDDH=VDDL=3.3V option. The disadvantage is that internal APLL regulators are bypassed and the APLL runs

directly from the VDDH supply, which leaves the device more susceptible to power supply noise. This susceptibility

can be mitigated using good power supply noise filtering and further mitigated with a dedicated LDO for the device.

The VDDH=2.5V, VDDL=1.8V option provides even lower power consumption than the VDDH=VDDL=2.5V option.

The disadvantages are (1) it requires two core power supply voltages, and (2) just like the VDDH=VDDL=2.5V case,

internal APLL regulators are bypassed and the APLL runs directly from the VDDH supply, which leaves the device

more susceptible to power supply noise. This susceptibility can be mitigated using good power supply noise filtering

and further mitigated with a dedicated LDO for the device.

See application note ZLAN-630 for power supply noise rejection performance.

5.15 Path 2 Signal Selection

In addition to the APLL, the device also provides a non-PLL path through the device called Path 2. See the block

diagram in Figure 1. Path 2 is essentially a built-in fanout buffer with its own input mux. Each bank of outputs can

be connected to the

APLL’s integer divider, the APLL’s fractional divider, or Path 2 using the appropriate field in the

OCMUX registers.

The Path 2 input mux can select any of inputs IC1 through IC3, a clock signal on XA, or the crystal driver circuit when

a crystal is connected to XA and XB.

The input to Path 2 can be controlled by a register field or a GPIO pin. When P2CR3.EXTSW=0, the P2CR3.MUX

When P2CR3.EXTSW=1, a GPIO pin controls the Path 2 input mux. When the GPIO pin is low, the mux selects the

input specified by P2CR3.MUX. When the GPIO pin is high, the mux selects the input specified by P2CR3.ALTMUX.

P2CR1.EXTSS specifies which GPIO pin controls this behavior.

The P2SR.SELREF real-

time status field indicates Path 2’s selected reference.

6. Register Descriptions

Table 4 shows the register map. In each register, bit 7 is the MSb and bit 0 is the LSb. Register addresses not listed

are reserved. B

its marked “—“ are reserved and must be written with 0. Writing other values to these registers may

put the device in a factory test mode resulting in undefined operation. Bits labeled “0” or “1” must be written with that

value for proper operation. Register fields with underlined names are read-only fields; writes to these fields have no

effect. All other fields are read-write. Register fields are described in detail in the register descriptions that follow

Table 4.

6.1

6.1.1

Status Bits

The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the

time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending

on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect. When set, some latched status

bits can cause an interrupt request if enabled to do so by corresponding interrupt enable bits. Status bits marked

“—

“ are reserved and must be ignored.

6.1.2

Configuration Fields

Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the

Configuration register bits marked “—“ are reserved and must be written with 0.

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