ZL30263 datasheet(75/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

XACR3

XA Input Clock Configuration Register 3

302h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

XBCAP[3:0]

XACAP[3:0]

Default

Bits 7 to 4: XB Internal Capacitor Selection (XBCAP[3:0]). Actual internal capacitance on the XB pin in pF is

approximately 6 + XBCAP. See section 5.3.2.

Bits 3 to 0: XA Internal Capacitor Selection (XACAP[3:0]). Actual internal capacitance on the XA pin in pF is

approximately 6 + XACAP. See section 5.3.2.

ICxCR1

Input Clock x Configuration Register 1

IC1: 303h, IC2: 304h, IC3: 305h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

POL

DISMON

VALTIME[2:0]

HSDIV[1:0]

Default

Bit 6: Input Polarity (POL). This field specifies which input clock edge the APLL will lock to. See section 5.5.1.

0 = Rising edge

1 = Falling edge

Bit 5: Disable Signal Going to the Monitor (DISMON).

0 = ICx signal is provided to the ICx monitor

1 = ICx signal is not provided to the ICx monitor

Bits 4 to 2: Input Validation Time (VALTIME[2:0]). The input clock monitor only declares the input clock valid if it

has no missing edges in the interval specified by this field. See section 5.5.2.

000 = 1 cycle

001 = 4 cycles

010 = 16 cycles

011 = 64 cycles

100 = 256 cycles

101 = 1024 cycles

110 - 111 = {unused values}

Bits 1 to 0: Input Clock High-Speed Divider (HSDIV[1:0]). This field specifies the divide value for the input clock

high-speed divider. See section 5.5.1.

00 = Divide by 1

01 = Divide by 2

10 = Divide by 4

11 = Divide by 8

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