ZL30263 datasheet(74/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

6.3.6

Input Clock Configuration Registers

XACR1

XA Input Clock Configuration Register 1

300h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

POL

DISMON

VALTIME[2:0]

HSDIV[1:0]

Default

Bit 6: Input Polarity (POL). This field specifies which input clock edge the APLL will lock to. See section 5.5.1.

0 = Rising edge

1 = Falling edge

Bit 5: Disable Signal Going to the Monitor (DISMON).

0 = XA signal is provided to the XA monitor

1 = XA signal is not provided to the XA monitor

Bits 4 to 2: Input Validation Time (VALTIME[2:0]). The input clock monitor only declares the XA input clock valid

if it has no missing edges in the interval specified by this field. See section 5.5.2.

000 = 1 cycle

001 = 4 cycles

010 = 16 cycles

011 = 64 cycles

100 = 256 cycles

101 = 1024 cycles

110 - 111 = {unused values}

Bits 1 to 0: Input Clock High-Speed Divider (HSDIV[1:0]). This field specifies the divide value for the XA input

clock divider. This field should not be set to 01 at the same time MCR2.DBL=1. See section 5.5.1.

00 = Divide by 1

01 = Divide by 2

10, 11 = {unused values}

XACR2

XA Input Clock Configuration Register 2

301h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

XOAMP[7:0]

Default

Bits 7 to 0: XO Amplifier Control (XOAMP[7:0]). Set this value as follows for the recommended 10pF crystal

(values in decimal). Contact Microchip apps support for XOAMP values for crystals with other load capacitances.

Crystal

Frequency (MHz)

Max Crystal Drive

100

W

200

W

300

W

152

136

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