ZL30263 datasheet(17/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

System software then writes the newFDIV value directly to the FDIV registers.

Note that any subsequent frequency changes are calculated using the same equation from the original FDIV0 value

and are not a function of the previous newFDIV value.

During NCO operation using the fractional output divider, FREM should be set to 0, FDEN should be set to 1 and

FBP should be set to 0.

5.5.7

Frequency Increment and Decrement

When ACR1.USEFDIV=0 t

he APLL’s feedback divider value can be incremented or decremented by values ranging

from approximately 1ppb to 500ppm. The value AID[23:0] x 27

is added to the APLL’s feedback divider value each

time the trigger specified by AIDCR.FISS changes state. AID[23:0] x 27

is subtracted from the APLL’s feedback

divider value each time the trigger specified by AIDCR.FDSS changes state. The value to be written to AID[23:0] s

as follows:

AID = round(AFBDIV0 * FFO/1e6 / 27)

where FFO is the desired fractional frequency offset (FFO) per increment or decrement step in ppm

AFBDIV0 is the nominal AFBDIV value, obtained by reading AFBDIV when AFBDL.RDCUR=0

The current APLL feedback divider value (i.e. the value after increments and decrements) can be read from the

AFBDIV registers when AFBDL.RDCUR=1. The original value of the AFBDIV registers before increments and

decrements can be read from the AFBDIV registers when AFBDL.RDCUR=0. Incrementing and decrementing only

occur when the APLL is locked (APLLSR.ALK=1). If the APLL loses lock, when it locks again the APLL sets its

feedback divider value back to the AFBDIV0 value. The system must be designed to ensure the current feedback

divider value stays within ±1000ppm of the AFBDIV0 value to avoid causing the APLL to lose lock. The maximum

increment/decrement is 500ppm. Frequency increment/decrement behavior is mutually exclusive with spread-

spectrum modulation (see section 5.5.8) because both behaviors use the AID registers. Frequency

increment/decrement is enabled when ACR1.ENFID=1. When ENFID is set to 0 the APLL feedback divider instantly

changes to the AFBDIV0 value. Therefore, to avoid a frequency jump on output clocks, system software should

increment or decrement back to the AFBDIV0 value before changing ENFID to 0.

5.5.8

Spread-Spectrum Modulation Mode

For EMI-sensitive applications such as PCI Express, the device can perform spread spectrum modulation (SSM). In

SSM the frequency of the output clock is continually varied over a narrow frequency range to spread the energy of

the signal and thereby reduce EMI. This mode is a special case of NCO mode.

Spread spectrum mode is enabled by the ASCR.ENSS bit or by a GPIO pin as specified by ASCR.SPRDSS.

5.5.8.1

Using the APLL’s Feedback Divider

When ACR1.USEFDIV=0 the device performs frequency modulation

by modulating the APLL’s feedback divider

value starting from the nominal value specified in the AFBDIV registers.

For center-spread applications (ASCR.DWNEN=0), the frequency modulation is triangle-wave center-spread of up

to ±0.5% deviation from the center frequency with modulation rate configurable from 25kHz to 55kHz. The spread

deviation and modulation rate are controlled by specifying an increment/decrement step in the AID registers and the

number of APLL input clock cycles to increment and decrement in the ASCNT registers. The values to be written to

the device are calculated as follows:

�� = �� (

��

4 ∗ ��

) − 2

�� = �� (

��

∗

�� ∗ 232

�� + 2

)

where FVCO is the

APLL”s VCO frequency in Hz,

FIN

is the input frequency at the APLL’s PFD in Hz,

FMOD is the spread-spectrum modulation frequency in Hz,

ZL30263 Datasheet(PDF) 17 Page - Microchip Technology

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