P5021 datasheet(51/155 Pages) NXP

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Pin assignments and reset states

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

Notes:

1. Recommend a weak pull-up resistor (2–10 k

Ω) be placed on this pin to OV

DD.

2. This pin is an open drain signal.

3. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k

Ω resistor. However, if the signal is

intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then

a pull up or active driver is needed.

4. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.

5. Recommend a weak pull-up resistor (2–10 k

Ω) be placed on this pin to BV

DD, to ensure no random chip select assertion due

to possible noise, and so forth.

6. This output is actively driven during reset rather than being three-stated during reset.

7. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

8. These pins are connected to the correspondent power and ground nets internally and may be connected as a differential pair

to be used by the voltage regulators with remote sense function.

9. These pins may be connected to a thermal diode monitoring device such as the ADT7461A only with a clear understanding

that proper thermal diode operation is not implied and the thermal diode feature may not be available in the production device.

11. Do not connect.

12. These are test signals for factory use only and must be pulled up (100

Ω–1 kΩ) to OV

DD for normal device operation.

13. Independent supplies derived from board VDD_PL (Core clusters, Platform, DDR) or SVDD (SerDes).

14. Recommend a pull-up resistor of 1-k

Ω be placed on this pin to OV

DD if I2C interface is used.

15. This pin requires an external 1-k

Ω pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively

driven.

16. For DDR3 and DDR3L, Dn_MDIC[0] is grounded through an 40.2-

Ω (half-strength mode) precision 1% resistor and

Dn_MDIC[1] is connected to GVDD through an 40.2-Ω (half-strength mode) precision 1% resistor. These pins are used for

automatic calibration of the DDR3 and DDR3L IOs.

18. These pins should be pulled up to 1.2V through a 180

Ω ± 1% resistor for EM2_MDC and a 330Ω ± 1% resistor for

EM2_MDIO.

20. Pin has a weak internal pull-up.

21. These pins should be pulled to ground (GND).

22. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage

levels. LVDD must be powered to use this interface.

23. This pin requires a 200-

Ω pull-up to XV

DD.

24. This pin requires a 200-

Ω pull-up to SV

DD.

25. This GPIO pin is on LVDD power plane, not OVDD.

26. Functionally, this pin is an I/O, but may act as an output only or an input only depending on the pin mux configuration defined

by the RCW.

27. See Section 3.6, “Connection recommendations,” for additional details on this signal.

28. This signal must be pulled low to GND.

30. Warning, incorrect voltage select settings can lead to irreversible device damage. See Section 3.2, “Supply power default

setting.”

31. SDHC_DAT[4:7] require CVDD = 3.3 V when muxed extended SDHC data signals are enabled via the RCW[SPI] field.

32. The cfg_xvdd_sel(LAD[26]) reset configuration pin must select the correct voltage that is being supplied on the XVDD pin.

Incorrect voltage select settings can lead to irreversible device damage.

Table 1. Pins listed by bus (continued)

Signal

Signal description

Package

pin number

type

Power

supply

Notes

P5021 Datasheet(PDF) 51 Page - NXP Semiconductors

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