P5021 datasheet(60/155 Pages) NXP

60 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

WARNING

Incorrect voltage select settings can lead to irreversible device damage. See Section 3.2,

“Supply power default setting.”

NOTE

From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_CA, or

VDD_PL supplies, the I/Os associated with that I/O supply may drive a logic one or zero

during power-up, and extra current may be drawn by the device.

2.3

Power-down requirements

The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be

started.

If performing secure boot fuse programming per Section 2.2, “Power-up sequencing,” it is required that POVDD = GND before

the system is power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in

Table 5.

VDD_PL and USB_VDD_1P0 must be ramped down simultaneously. USB_VDD_1P8_DECAP should starts ramping down only

after USB_VDD_3P3 is below 1.65 V.

2.4

Power characteristics

This table shows the power dissipations of the VDD_CA, SVDD, and VDD_PL supply for various operating platform clock

frequencies versus the core and DDR clock frequencies for the chip.

Table 6. Power dissipation

Power

Mode

Core

freq

(MHz)

Plat

freq

(MHz)

DDR

data

rate

(MHz)

FM freq

(MHz)

VDD_PL,

SVDD

(V)

VDD_CA

(V)

Junction

temp

(

°C)

Core

and plat-

form

power1

(W)

VDD_PL

power

(W)

VDD_CA

power

(W)

SVDD

power

(W)

Note

Typical

2200

800

1600

600

1.0

1.2

—

Thermal

———

—

Maximum

2.2

Typical

2000

700

1333

600

1.0

1.1

—

Thermal

105

———

—

Maximum

2.2

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