P5021 datasheet(96/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

2.17.2

JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 28 through Figure 31.

This figure provides the AC test load for TDO and the boundary-scan outputs of the device.

Figure 28. AC test load for the JTAG interface

Table 55. JTAG AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

JTAG external clock frequency of operation

fJTG

033.3

MHz

—

JTAG external clock cycle time

tJTG

—

JTAG external clock pulse width measured at 1.4 V

tJTKHKL

—

JTAG external clock rise and fall times

tJTGR/tJTGF

—

TRST assert time

tTRST

—

Input setup times

tJTDVKH

—ns

—

Boundary-scan USB only

Boundary-scan except USB

TMS

TDI

Input hold times

tJTDXKH

—

Output valid times

tJTKLDV

—

Boundary-scan data

TDO

—

Output hold times

tJTKLDX

0—

Notes:

1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing

(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to

the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)

reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The

output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load. Time-of-flight delays must

be added for trace lengths, vias, and connectors in the system.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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