P5021 datasheet(79/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

This table provides the MII transmit AC timing specifications.

This figure shows the MII transmit AC timing diagram.

Figure 15. MII transmit AC timing diagram

This table provides the MII receive AC timing specifications.

Table 34. MII transmit AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

399.96

400

400.04

TX_CLK clock period 100 Mbps

tMTX

39.996

40.004

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

—

TX_CLK data clock rise (20%–80%)

tMTXR

1.0

—

4.0

TX_CLK data clock fall (80%–20%)

tMTXF

1.0

—

4.0

Table 35. MII Receive AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

RX_CLK clock period 10 Mbps

tMRX

399.96

400

400.04

RX_CLK clock period 100 Mbps

tMRX

39.996

40.004

RX_CLK duty cycle

tMRXH/tMRX

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

tMRDVKH

10.0

—

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

tMRDXKH

10.0

—

RX_CLK clock rise (20%-80%)

tMRXR

1.0

—

4.0

RX_CLK clock fall time (80%-20%)

tMRXF

1.0

—

4.0

Note: The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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