P5021 datasheet(54/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

Input voltage7

DDR3 and DDR3L DRAM signals

MVIN

–0.3 to (GVDD + 0.3)

2, 7

DDR3 and DDR3L DRAM reference

MVREF

–0.3 to (GVDD/2+ 0.3)

2, 7

Ethernet signals (except EMI2)

LVIN

–0.3 to (LVDD + 0.3)

3, 7

eSPI, eSHDC

CVIN

–0.3 to (CVDD + 0.3)

4, 7

Enhanced local bus signals

BVIN

–0.3 to (BVDD + 0.3)

5, 7

DUART, I2C, DMA, MPIC, GPIO, system

control and power management, clocking,

debug, I/O voltage select, and JTAG I/O

voltage

OVIN

–0.3 to (OVDD + 0.3)

6, 7

SerDes signals

XVIN

–0.4 to (XVDD + 0.3)

USB PHY transceiver signals

USB_VIN_3P3

–0.3 to

(USB_VDD_3P3 + 0.3)

Ethernet management interface 2 (EMI2)

signals

—

–0.3 to (1.2 + 0.3)

Storage junction temperature range

Tstg

–55 to 150

°C—

Notes:

1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only; functional operation

at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to

the device.

2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

4. Caution: CVIN must not exceed CVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

5. Caution: BVIN must not exceed BVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

6. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

7. (C,X,B,G,L,O)VIN may overshoot (for VIH) or undershoot (for VIL) to the voltages and maximum duration shown in Figure 7.

8. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels.

LVDD must be powered to use this interface.

9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the

sense pin.

10. Implementation may choose either VDD_PL pin for feedback loop. If the platform and core groups are supplied by a single

regulator, it is recommended that VDD_CA be used.

11. VDD_PL voltage must not exceed VDD_CA.

Table 2. Absolute maximum operating conditions1 (continued)

Parameter

Symbol

Maximum value

Unit

Notes

P5021 Datasheet(PDF) 54 Page - NXP Semiconductors

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