P5021 datasheet(52/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

Electrical characteristics

This section provides the AC and DC electrical specifications for the chip. The chip is currently targeted to these specifications,

some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1

Overall DC electrical characteristics

This section describes the ratings, conditions, and other electrical characteristics.

2.1.1

Absolute maximum ratings

This table provides the absolute maximum ratings.

33. See Section 2.2, “Power-up sequencing and Section 5, “Security fuse processor,” for additional details on this signal.

35. Pin must NOT be pulled down by a resistor or the component it is connected to during power-on reset.

36. This pin should be connected to GND through a 10k

Ω ± 0.1% resistor with a low temperature coefficient of ≤ 25ppm/°C for

bias generation.

37. A 1uF to 1.5uF capacitor connected to GND is required on this signal. A list of recommended capacitors are shown in

Section 3.6.4.2, “USBn_VDD_1P8_DECAP capacitor options.”

38. A divider network is required on this signal. See Section 3.6.4.1, “USB divider network.”

39. For systems which boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pullup on LGPL4 is

required.

40. Functionally, this pin is an input, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.

41. If migration from a P4 device, this pin is allowed to be powered by AVDD_CC2. If not migrating, do not connect.

42. The VDD_VID_CA_CB pins are inputs at POR. If a voltage regulator is connected directly to the VID_VDD_CA_CB pins,

customers need to put weak pull-ups or pull-downs on their board so that their voltage regulator drives a guaranteed-to-work

voltage with the cores configured to run at a safe frequency for that voltage. This is needed so that a working voltage can be

applied until the operating voltage is determined (for example, so that PLLs can begin to lock, and so on, during this time frame

or while the voltage is ramping). The safe boot voltage for the chip is 1.1 V. Note that the P5021 does not require VID to meet

it's performance and power envelope. All power rails should be fixed at the operating values specified in Table 3.

“Recommended operating conditions.”

43. VDD_LL should be connected directly to VDD_PL.

44. Normally tied to GND. See the applicable migration application note if moving from P3041 (AN4395) or P5020/P5010

(AN4400).

Table 2. Absolute maximum operating conditions1

Parameter

Symbol

Maximum value

Unit

Notes

Core group A (core 0,1) supply voltage

VDD_CA

–0.3 to 1.32

9,11

Platform supply voltage

VDD_PL

–0.3 to 1.1

9,10,

PLL supply voltage (core, platform, DDR)

AVDD

–0.3 to 1.1

—

PLL supply voltage (SerDes, filtered from SVDD)AVDD_SRDS

–0.3 to 1.1

—

Table 1. Pins listed by bus (continued)

Signal

Signal description

Package

pin number

type

Power

supply

Notes

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