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P5021 Datasheet(PDF) 73 Page - NXP Semiconductors |
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P5021 Datasheet(HTML) 73 Page - NXP Semiconductors |
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73 / 155 page  Electrical characteristics P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 73 This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 10. tDDKHMH timing diagram This figure shows the DDR3 and DDR3L SDRAM output timing diagram. Figure 11. DDR3 and DDR3L output timing diagram MDQS[n] MCK[n] MCK[n] tMCK tDDKHMH(max) tDDKHMH(min) MDQS[n] ADDR/CMD tDDKHAS, tDDKHCS tDDKLDS tDDKHDS MDQ[x] MDQS[n] MCK[n] MCK[n] tMCK tDDKLDX tDDKHDX D1 D0 tDDKHAX, tDDKHCX Write A0 NOOP tDDKHME tDDKHMH tDDKHMP |
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