 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
P5021 Datasheet(PDF) 1 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P5021 Datasheet(HTML) 1 Page - NXP Semiconductors |
|
|
1 / 155 page  Freescale Semiconductor Data Sheet: Technical Data © 2013-2014 Freescale Semiconductor, Inc. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. The P5021 QorIQ integrated communication processor combines two Power Architecture® processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design. The chip includes the following function and features: • Two e5500 Power Architecture cores – Each core has a backside 512 KB L2 cache with ECC – Three levels of instructions: user, supervisor, and hypervisor – Independent boot and reset – Secure boot capability • CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints • Frontside 2 MB CoreNet platform cache with ECC • CoreNet bridges between the CoreNet fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces • Two 10-Gigabit Ethernet (XAUI) controllers • Ten 1-Gigabit Ethernet controllers – SGMII, 2.5Gb/s SGMII and RGMII interfaces • Two 64-bit DDR3/3L SDRAM memory controllers with ECC • Multicore programmable interrupt controller (PIC) •Four I2C controllers • Four 2-pin UARTs or two 4-pin UARTs • Two 4-channel DMA engines • Enhanced local bus controller (eLBC) • Three PCI Express 2.0 controllers/ports • Two serial ATA (SATA) 2.0 controllers • Enhanced secure digital host controller (SD/MMC) • Enhanced serial peripheral interface (eSPI) • Two high-speed USB 2.0 controllers with integrated PHYs • RAID 5 and 6 storage accelerator with support for end-to-end data protection information • Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: – Frame Manager (FMan) for packet parsing, classification, and distribution – Queue Manager (QMan) for scheduling, packet sequencing and congestion management – Hardware Buffer Manager (BMan) for buffer allocation and deallocation – Encryption/Decryption • 1295 FC-PBGA package This figure shows the major functional units within the chip. P5021 QorIQ Integrated Processor Data Sheet Document Number: P5021 Rev. 1, 05/2014 P5021 FC-PBGA–1295 37.5 mm × 37.5 mm |
Similar Part No. - P5021 |
|
Similar Description - P5021 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
