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P5021 Datasheet(PDF) 87 Page - NXP Semiconductors

Part # P5021
Description  P5021 QorIQ Integrated Processor Data Sheet
PDF  155 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

P5021 Datasheet(HTML) 87 Page - NXP Semiconductors

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Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
87
2.13.1
USB DC electrical characteristics
This table provides the DC electrical characteristics for the USB interface at USB_VDD_3P3 = 3.3 V.
2.13.2
USB AC electrical specifications
This table provides the USB clock input (USBn_CLKIN) AC timing specifications.
This figure provides the USB AC test load.
Figure 22. USB AC test load
2.14
Enhanced local bus interface (eLBC)
This section describes the DC and AC electrical specifications for the enhanced local bus interface.
Table 44. USB DC electrical characteristics (USB_VDD_3P3 = 3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage1
VIH
2.0
V
1
Input low voltage
VIL
—0.8
V
1
Input current (USB_VIN_3P3 = 0 V or USB_VIN_3P3 =
USB_VDD_3P3)
IIN
—±40
μA2
Output high voltage (USB_VDD_3P3 = min, IOH = –2 mA)
VOH
2.8
V
Output low voltage (USB_VDD_3P3 = min, IOL = 2 mA)
VOL
—0.3
V
Notes:
1. The min VILand max VIH values are based on the respective min and max USB_VIN_3P3 values found in Table 3.
2. The symbol USB_VIN_3P3, in this case, represents the USB_VIN_3P3 symbol referenced in Section 2.1.2, “Recommended
operating conditions.”
Table 45. USBn_CLKIN AC timing specifications
For recommended operating conditions, see Table 3.
Parameter/Condition
Conditions
Symbol
Min
Typ
Max
Unit
Frequency range
fUSB_CLK_IN
—24—
MHz
Clock frequency tolerance
tCLK_TOL
–0.005
0
0.005
%
Reference clock duty cycle
Measured at 1.6 V
tCLK_DUTY
40
50
60
%
Total input jitter/time interval
error
Peak-to-peak value measured with a
second-order high-pass filter of 500 kHz
bandwidth
tCLK_PJ
——
5
ps
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω



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