P5021 datasheet(64/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

This table provides the system clock (SYSCLK) AC timing specifications.

2.6.2

Spread-spectrum sources recommendations

Spread-spectrum clock sources is an increasingly popular way to control electromagnetic interference emissions (EMI) by

spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and

government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter

specification given in Table 13 considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output

jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns;

the chip is compatible with spread spectrum sources if the recommendations listed in Table 13 are observed.

CAUTION

The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which

the processor is operated at its maximum rated core/platform/DDR frequency should avoid

violating the stated limits by using down-spreading only.

Table 12. SYSCLK AC timing specifications

For recommended operating conditions, see Table 3.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

SYSCLK frequency

fSYSCLK

100

—

166

MHz

1, 2

SYSCLK cycle time

tSYSCLK

—

1, 2

SYSCLK duty cycle

tKHK / tSYSCLK

—

SYSCLK slew rate

—

V/ns

SYSCLK peak period jitter

—

150

—

SYSCLK jitter phase noise

—

500

KHz

AC Input Swing Limits at 3.3 V OVDD

ΔV

1.9

—

Notes:

1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency, do not exceed their

respective maximum or minimum operating frequencies.

2. Measured at the rising edge and/or the falling edge at OVDD/2.

3. Slew rate as measured from ±0.3

ΔV

AC at center of peak to peak voltage at clock input.

4. Phase noise is calculated as FFT of TIE jitter.

Table 13. Spread-spectrum clock source recommendations

For recommended operating conditions, see Table 3.

Parameter

Min

Max

Unit

Notes

Frequency modulation

—

kHz

—

Frequency spread

—

1.0

1, 2

Notes:

1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and

maximum specifications given in Table 12.

2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.

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