P5021 datasheet(12/155 Pages) NXP

12 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Pin assignments and reset states

Freescale Semiconductor

D1_MDQS7

Data Strobe

AT11

I/O

GVDD

—

D1_MDQS8

Data Strobe

I/O

GVDD

—

D1_MBA0

Bank Select

AA8

GVDD

—

D1_MBA1

Bank Select

Y10

GVDD

—

D1_MBA2

Bank Select

GVDD

—

D1_MA00

Address

GVDD

—

D1_MA01

Address

GVDD

—

D1_MA02

Address

GVDD

—

D1_MA03

Address

GVDD

—

D1_MA04

Address

U10

GVDD

—

D1_MA05

Address

GVDD

—

D1_MA06

Address

GVDD

—

D1_MA07

Address

GVDD

—

D1_MA08

Address

GVDD

—

D1_MA09

Address

GVDD

—

D1_MA10

Address

AA7

GVDD

—

D1_MA11

Address

GVDD

—

D1_MA12

Address

GVDD

—

D1_MA13

Address

AE8

GVDD

—

D1_MA14

Address

GVDD

—

D1_MA15

Address

GVDD

—

D1_MWE

Write Enable

AB8

GVDD

—

D1_MRAS

Row Address Strobe

AA10

GVDD

—

D1_MCAS

Column Address Strobe

AC10

GVDD

—

D1_MCS0

Chip Select

AC9

GVDD

—

D1_MCS1

Chip Select

AE9

GVDD

—

D1_MCS2

Chip Select

AB9

GVDD

—

D1_MCS3

Chip Select

AF9

GVDD

—

D1_MCKE0

Clock Enable

P10

GVDD

—

D1_MCKE1

Clock Enable

R10

GVDD

—

D1_MCKE2

Clock Enable

GVDD

—

D1_MCKE3

Clock Enable

GVDD

—

D1_MCK0

Clock

GVDD

—

D1_MCK1

Clock

GVDD

—

Table 1. Pins listed by bus (continued)

Signal

Signal description

Package

pin number

type

Power

supply

Notes

P5021 Datasheet(PDF) 12 Page - NXP Semiconductors

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