P5021 datasheet(72/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

NOTE

For the ADDR/CMD setup and hold specifications in Table 25, it is assumed that the clock

control register is set to adjust the memory clocks by ½ applied cycle.

MDQ/MECC/MDM output setup with respect to

MDQS

tDDKHDS,

tDDKLDS

1600 MT/s data rate

200

—

1333 MT/s data rate

250

—

1200 MT/s data rate

275

—

1066 MT/s data rate

300

—

800 MT/s data rate

375

—

MDQ/MECC/MDM output hold with respect to

MDQS

tDDKHDX,

tDDKLDX

1600 MT/s data rate

200

—

1333 MT/s data rate

250

—

1200 MT/s data rate

275

—

1066 MT/s data rate

300

—

800 MT/s data rate

375

—

MDQS preamble

tDDKHMP

0.9

× t

MCK

—ns

—

MDQS post-amble

tDDKHME

0.4

× t

MCK

0.6

× t

MCK

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay

as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters

have been set to the same adjustment value. See the applicable chip reference manual for a description and explanation of

the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

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