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P5021 Datasheet(PDF) 67 Page - NXP Semiconductors

Part # P5021
Description  P5021 QorIQ Integrated Processor Data Sheet
PDF  155 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

P5021 Datasheet(HTML) 67 Page - NXP Semiconductors

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Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
67
2.9.1
DDR3 and DDR3L SDRAM interface DC electrical characteristics
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3
SDRAM.
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L
SDRAM.
Table 18. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)
1
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
I/O reference voltage
MVREF
0.49
× GV
DD
0.51
× GV
DD
V2, 3, 4
Input high voltage
VIH
MVREF + 0.100
GVDD
V5
Input low voltage
VIL
GND
MVREF –0.100
V
5
I/O leakage current
IOZ
–50
50
μA6
Notes:
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed the MVREF DC level by more than ±1% of the DC value (that is, ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC
level of MVREF.
4. The voltage regulator for MVREF must meet the specifications stated in Table 21.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V
V
OUT GVDD.
Table 19. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)
1
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
I/O reference voltage
MVREF
0.49
× GV
DD
0.51
× GV
DD
V2, 3, 4
Input high voltage
VIH
MVREF + 0.090
GVDD
V5
Input low voltage
VIL
GND
MVREF –0.090
V
5



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