P5021 datasheet(99/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

This figure provides the AC test load for the I2C.

Figure 32. I2C AC test load

This figure shows the AC timing diagram for the I2C bus.

Figure 33. I2C bus AC timing diagram

Noise margin at the LOW level for each connected

device (including hysteresis)

VNL

0.1

× OV

—V

—

Noise margin at the HIGH level for each connected

device (including hysteresis)

VNH

0.2

× OV

—V

—

Capacitive load for each bus line

—

400

—

Notes:

1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing (I2)

with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the

high (H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the START

condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH

symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative

to the tI2C clock reference (K) going to the high (H) state or setup time.

2. The requirements for I2C frequency calculation must be followed. See Freescale application note AN2919, “Determining the

I2C Frequency Divider Ratio for SCL.”

3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal)

to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When

the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are

balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time

is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter,

application note AN2919 referred to in note 2 above is recommended.

4. The maximum tI2OVKL must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.

Table 57. I2C AC timing specifications (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SDA

SCL

tI2SXKL

tI2CL

tI2CH

tI2DXKL,tI2OVKL

tI2DVKH

tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

tI2KHDX

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