P5021 datasheet(71/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

2.9.2.2

DDR3 and DDDR3L SDRAM interface output AC timing specifications

This table contains the output AC timing targets for the DDR3 SDRAM interface.

Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

MCK[n] cycle time

tMCK

1.25

2.5

ADDR/CMD output setup with respect to MCK

tDDKHAS

1600 MT/s data rate

0.495

—

1333 MT/s data rate

0.606

—

1200 MT/s data rate

0.675

—

1066 MT/s data rate

0.744

—

800 MT/s data rate

0.917

—

ADDR/CMD output hold with respect to MCK

tDDKHAX

1600 MT/s data rate

0.495

—

1333 MT/s data rate

0.606

—

1200 MT/s data rate

0.675

—

1066 MT/s data rate

0.744

—

800 MT/s data rate

0.917

—

MCS[n] output setup with respect to MCK

tDDKHCS

1600 MT/s data rate

0.495

—

1333 MT/s data rate

0.606

—

1200 MT/s data rate

0.675

—

1066 MT/s data rate

0.744

—

800 MT/s data rate

0.917

—

MCS[n] output hold with respect to MCK

tDDKHCX

1600 MT/sdata rate

0.495

—

1333 MT/s data rate

0.606

—

1200 MT/s data rate

0.675

—

1066 MT/sdata rate

0.744

—

800 MT/s data rate

0.917

—

MCK to MDQS Skew

tDDKHMH

> 1066 MT/s data rate

–0.245

0.245

800 MT/s data rate

–0.375

0.375

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