P5021 datasheet(58/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

2.1.3

Output driver characteristics

This table provides information about the characteristics of the output driver strengths. The values are preliminary estimates.

2.2

Power-up sequencing

The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. These

requirements are as follows for power up:

1. Bring up OVDD, LVDD, BVDD, CVDD, and USB_VDD_3P3. Drive POVDD = GND.

— PORESET input must be driven asserted and held during this step

— IO_VSEL inputs must be driven during this step and held stable during normal operation.

—USB_VDD_3P3 rise time (10% to 90%) has a minimum of 350 μs.

2. Bring up VDD_PL, VDD_CA, SVDD, AVDD (cores, platform, DDR, SerDes) and USB_VDD_1P0. VDD_PL and

USB_VDD_1P0 must be ramped up simultaneously.

3. Bring up GVDD and XVDD.

4. Negate PORESET input as long as the required assertion/hold time has been met per Table 15.

5. For secure boot fuse programming: After negation of PORESET, drive POVDD = 1.5 V after a required minimum

delay per Table 5. After fuse programming is completed, it is required to return POVDD = GND before the system is

power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in

Table 5. See Section 5, “Security fuse processor,” for additional details.

WARNING

Only two secure boot fuse programming events are permitted per lifetime of a device.

No activity other than that required for secure boot fuse programming is permitted while

POVDD driven to any voltage above GND, including the reading of the fuse block. The

reading of the fuse block may only occur while POVDD = GND.

Table 4. Output drive capability

Driver type

Output impedance (

Ω)

(Nominal) supply

voltage

Notes

Local bus interface utilities signals

BVDD = 3.3 V

BVDD = 2.5 V

BVDD = 1.8 V

—

DDR3 signal

20 (full-strength mode)

40 (half-strength mode)

GVDD = 1.5 V

DDR3L signal

20 (full-strength mode)

40 (half-strength mode)

GVDD = 1.35 V

eTSEC/10/100 signals

LVDD = 3.3 V

LVDD = 2.5 V

—

DUART, system control, JTAG

OVDD = 3.3 V

—

I2C45

OVDD = 3.3 V

—

eSPI and SD/MMC

CVDD = 3.3 V

CVDD = 2.5 V

CVDD = 1.8 V

—

Note:

1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GVDD (min).

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