P5021 datasheet(65/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

2.6.3

Real time clock timing

The real time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an

input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum pulse

width of the RTC signal should be greater than 16

× the period of the platform clock with a 50% duty cycle. There is no minimum

RTC frequency; RTC may be grounded if not needed.

2.6.4

dTSEC gigabit Ethernet reference clock timing

This table provides the dTSEC gigabit Ethernet reference clocks AC timing specifications.

2.6.5

Other input clocks

A description of the overall clocking of this device is available in the applicable chip reference manual in the form of a clock

subsystem block diagram. For information on the input clock requirements of functional blocks sourced external of the device,

such as SerDes, Ethernet Management, eSDHC, Local bus, see the specific interface section.

2.7

RESET initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the

RESET initialization AC timing specifications.

Table 14. EC_GTX_CLK125 AC timing specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

tG125

—125

—

MHz

—

EC_GTX_CLK125 cycle time

tG125

—8

—

EC_GTX_CLK125 rise and fall time

LVDD = 2.5 V

LVDD = 3.3 V

tG125R/tG125F

——

0.75

1.0

EC_GTX_CLK125 duty cycle

1000Base-T for RGMII

tG125H/tG125

—

EC_GTX_CLK125 jitter

—

± 150

Note:

1. Rise and fall times for EC_GTX_CLK125 are measured from 20% to 80% (rise time) and 80% to 20% (fall time) of LVDD.

2. EC_GTX_CLK125 is used to generate the GTX clock for the dTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty

cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the dTSEC

GTX_CLK. See Section 2.12.2.3, “RGMII AC timing specifications,” for duty cycle for 10Base-T and 100Base-T reference

clock.

Table 15. RESET initialization timing specifications

Parameter

Min

Max

Unit1

Notes

Required assertion time of PORESET

1—

Required input assertion time of HRESET

—

SYSCLKs

1, 2

Input setup time for POR configurations with respect to negation of

PORESET

—

SYSCLKs

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