P5021 datasheet(59/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

WARNING

Only 100,000 POR cycles are permitted per lifetime of a device.

WARNING

While VDD is ramping, current may be supplied from VDD through the P5021 to GVDD.

Nevertheless, GVDD from an external supply should follow the sequencing described

above.

All supplies must be at their stable values within 75 ms.

Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered

sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step

reach 10% of theirs.

This figure provides the POVDD timing diagram.

Figure 8. POVDD timing diagram

This table provides information on the power-down and power-up sequence parameters for POVDD.

To guarantee MCKE low during power up, the above sequencing for GVDD is required. If there is no concern about any of the

DDR signals being in an indeterminate state during power up, the sequencing for GVDD is not required.

Table 5. POVDD timing

Driver type

Min

Max

Unit

Notes

tPOVDD_DELAY

100

—

SYSCLKs

tPOVDD_PROG

0—

μs2

tPOVDD_VDD

0—

μs3

tPOVDD_RST

0—

μs4

Notes:

1. Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90%

OVDD to 10% POVDD ramp up.

2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD

is stable at 1.5 V. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to

any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD =

GND. After fuse programming is completed, it is required to return POVDD = GND.

3. Delay required from POVDD ramp down complete to VDD_PL ramp down start. POVDD must be grounded to minimum 10%

POVDD before VDD_PL is at 90% VDD.

4. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD

before PORESET assertion reaches 90% OVDD.

5. Only two secure boot fuse programming events are permitted per lifetime of a device.

tPOVDD_PROG

tPOVDD_DELAY

POVDD

VDD_PL

PORESET

tPOVDD_RST

Fuse programming 1

90% OVDD

10% POVDD

90% VDD_PL

tPOVDD_VDD

NOTE: POVDD must be stable at 1.5 V prior to initiating fuse programming.

90% OVDD

P5021 Datasheet(PDF) 59 Page - NXP Semiconductors

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