P5021 datasheet(105/155 Pages) NXP

105 / 155 page

Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

105

— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.

Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock

receiver operate in different common mode voltages. The SerDes reference clock receiver in this connection

scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing

below and above the common mode voltage (SGND). Figure 38 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

Figure 38. Differential reference clock input DC requirements (external AC-coupled)

•

Single-Ended Mode

— The reference clock can also be single-ended. The SD_REF_CLKn input amplitude (single-ended swing) must be

between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SD_REF_CLKn either left unconnected or

tied to ground.

— The SD_REF_CLKn input average voltage must be between 200 and 400 mV. Figure 39 shows the SerDes

reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled

externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused

phase (SD_REF_CLKn) through the same source impedance as the clock input (SD_REF_CLKn) in use.

Figure 39. Single-ended reference clock input DC requirements

SD_REF_CLKn

Vcm

200 mV < Input Amplitude or Differential Peak < 800 mV

Vmax

< Vcm + 400 mV

Vmin

> Vcm – 400 mV

SD_REF_CLKn

400 mV

< SD_REF_CLKn Input Amplitude < 800 mV

P5021 Datasheet(PDF) 105 Page - NXP Semiconductors