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MMPF0100 Datasheet(PDF) 115 Page - NXP Semiconductors

Part # MMPF0100
Description  14 channel configurable power management integrated circuit
PDF  136 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0100 Datasheet(HTML) 115 Page - NXP Semiconductors

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NXP Semiconductors
115
PF0100
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
F5
OTP SPARE4_3
R/W
8'b0000_0xxx
––
–
–
–
RSVD
00
0
0
0
x
x
x
F6
OTP SPARE6_2
R/W
8'b0000_00xx
––
–
–
––
RSVD
00
0
0
00
x
x
F7
OTP SPARE7_1
R/W
8'b0000_0xxx
––
–
–
–
–
–
RSVD
00
0
0
0
x
x
x
FE
OTP DONE
R/W
8'b0000_000x
––
–
–
–––
OTP_DONE
00
0
0
000
x
FF
OTP I2C ADDR
R/W
8'b0000_0xxx
––
–
–
I2C_SLV
ADDR[3]
I2C_SLV ADDR[2:0]
00
0
0
1
x
x
x
Notes
83.
In the MMPF0100 FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1
for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In MMPF0100A, the XOR function is removed. It is
required to set all of the FUSE_PORx bits to be able to load the fuses.
Table 138. Extended Page 2
Address
Register name
TYPE
Default
BITS[7:0]
7
6
5
4
3
2
1
0
81
SW1AB PWRSTG
R/W
8'b1111_1111
RSVD
RSVD
RSVD
RSVD
RSVD
SW1AB_PWRSTG[2:0]
1
1
1
1
111
1
82
PWRSTG RSVD
R
8'b0000_0000
PWRSTGRSVD
0
0
0
0
000
0
83
SW1C PWRSTG
R
8'b1111_1111
RSVD
RSVD
RSVD
RSVD
RSVD
SW1C_PWRSTG[2:0]
1
1
1
1
111
1
84
SW2 PWRSTG
R
8'b1111_1111
RSVD
RSVD
RSVD
RSVD
RSVD
SW2_PWRSTG[2:0]
1
1
1
1
111
1
85
SW3A PWRSTG
R
8'b1111_1111
RSVD
RSVD
RSVD
RSVD
RSVD
SW3A_PWRSTG[2:0]
1
1
1
1
111
1
86
SW3B PWRSTG
R
8'b1111_1111
RSVD
RSVD
RSVD
RSVD
RSVD
SW3B_PWRSTG[2:0]
1
1
1
1
111
1
87
SW4 PWRSTG
R
8'b0111_1111
FSLEXT_
THERM_
DISABLE
PWRGD_
SHDWN_
DISABLE
RSVD
RSVD
RSVD
SW4_PWRSTG[2:0]
0
0
1
1
111
1
88
PWRCTRL OTP
CTRL
R/W
8'b0000_0001
––
–
–
–
–
PWRGD_EN
OTP_
SHDWN_EN
0
0
0
0
000
1
8D
I2C WRITE
ADDRESS TRAP
R/W
8'b0000_0000
I2C_WRITE_ADDRESS_TRAP[7:0]
0
0
0
0
000
0
Table 137. Extended page 1 (continued)
Address
Register name
TYPE
Default
BITS[7:0]
7
6
5
4
3
2
1
0



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