TDP0604 datasheet(34/65 Pages) TI

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8.4.1.2 Pin Strap Modes

In pin-strap mode, the SCL/CFG0 and the SDA/CFG1 pins will be used to control the HDMI 1.4 termination, lane

SWAP function, and the DisplayPort mode as described in Table 8-13 and Table 8-14.

Table 8-13. SCL/CFG0 Pin in Pin-Strap Mode

SCL/CFG0 Pin

AC_EN Pin

TDP0604 Function

HDMI 1.4 termination is open if HDMI clock

frequency ≤ fHDMI14_open

HDMI 1.4 termination is ≈300-Ω if HDMI clock

frequency ≥ fHDMI14_300

HDMI 1.4 termination is ≈300-Ω

Normal HDMI. Function determined by

MODE pin.

DisplayPort mode. DDC snoop disabled. All

four lanes enabled when HPD_IN is high.

Table 8-14. SDA/CFG1 Pin in Pin-Strap Mode

SDA/CFG1 Pin

TDP0604 Function

Normal Lane ordering

Lane Swap enabled.

Note

The SCL/CFG0 is the only two-level pin that is continuously sampled in pin-strap mode. AC_EN,

HPDOUT_SEL, and SDA/CFG1 will not be continuously sampled in pin-strap mode unless indicated

otherwise.

8.4.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description

The TDP0604 will always use the sampled state of EQ[1:0] pins when operating in either HDMI 1.4 and HDMI

2.0. The amount of EQ applied is determined by the CTLE Map used (refer to Section 8.3.8).

If TDP0604 is configured for limited redriver mode, the OUT_D[2:0] and OUT_CLKP/N levels will be fixed based

on the sampled state of TXSWG pin (refer to Table 8-12) and TXPRE pin (refer to Table 8-11).

If TDP0604 is configured for linear redriver mode, OUT_D[2:0] and OUT_CLK will be a linear function of the

input signals.

Table 8-15. MODE Pin Function

MODE Pin Level

Description

Pin Strap with DDC Buffer enabled

Pin Strap with DDC Buffer disabled.

I2C mode

Reserved.

Note

In source application, it is recommended to use limited redriver mode for both HDMI 1.4 and HDMI

2.0.

TDP0604

SLLSFJ8 – DECEMBER 2021

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