TDP0604 datasheet(39/65 Pages) TI

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9. The TDP0604 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master

after each byte transfer; the I2C master acknowledges reception of each data byte transfer.

10. If an ACK is received, the TDP0604 transmits the next byte of data as long as master provides the clock. If a

NAK is received, the TDP0604 stops providing data and waits for a stop condition (P).

11. The master terminates the read operation by generating a stop condition (P).

Slave Address

Write

Ack

Start

Stop

Figure 8-14. I2C Write without data

The following procedure should be followed for setting a starting sub-address for I2C reads (refer to Figure 8-14).

1. The master initiates a write operation by generating a start condition (S), followed by the TDP0604 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TDP0604 acknowledges the address cycle.

3. The master presents the register offset within TDP0604 to be written, consisting of one byte of data,

MSB-first.

4. The TDP0604 acknowledges the register offset cycle.

5. The master terminates the write operation by generating a stop condition (P).

Note

After initial power-up, if no register offset is included for the read procedure (refer to Figure 8-12), then

reads start at register offset 00h and continue byte by byte through the registers until the I2C master

terminates the read operation. During a read operation, the TDP0604 auto-increments the I2C internal

the I2C master.

8.6 Register Maps

8.6.1 TDP0604 Registers

TDP0604 Registers lists the memory-mapped registers for the TDP0604 registers. All register offset addresses

not listed in TDP0604 Registers should be considered as reserved locations and the register contents should not

be modified.

Table 8-19. TDP0604 Registers

Offset

Acronym

Section

REV_ID

Revision ID

Section 8.6.1.1

PD_RST

Power Down and Reset control

Section 8.6.1.2

MISC_CONTROL

Misc Control

Section 8.6.1.3

GBL_SLEW_CTRL

Global TX Slew control for data lanes in

HDMI1.4 and 2.0

Section 8.6.1.4

GBL_SLEW_CTRL2

Global TX Slew control for data and clock

Section 8.6.1.5

GBL_CTRL1

Global control

Section 8.6.1.6

GBL_CTLE_CTRL

Global CTLE control

Section 8.6.1.7

10h

DDC_CFG

DDC Buffer controls

Section 8.6.1.8

11h

LANE_ENABLE

Lane enables

Section 8.6.1.9

12h

CLK_CONFIG1

CLK lane TX swing control

Section 8.6.1.10

14h

D0_CONFIG1

D0 lane TX swing and FFE control

Section 8.6.1.11

15h

D0_CONFIG2

D0 lane RX EQ control

Section 8.6.1.12

16h

D1_CONFIG1

D1 lane TX swing and FFE control

Section 8.6.1.13

17h

D1_CONFIG2

D1 lane RX EQ control

Section 8.6.1.14

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TDP0604

SLLSFJ8 – DECEMBER 2021

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