TDP0604 datasheet(4/65 Pages) TI

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Table 5-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

IN_D2n

Channel 2 differential negative input.

HPD_OUT

Hot plug detect output to source side. If not used, then this pin can be left floating. If

used, then it is recommended to have a external 220k resistor to GND on this pin.

IN_D1p

Channel 1 differential positive input.

IN_D1n

Channel 1 differential negative input.

VIO

Voltage supply for I/Os. Refer to Table 8-2.

IN_D0p

Channel 0 differential positive input.

IN_D0n

Channel 0 differential negative input.

MODE

4-Level

(PU/PD)

Mode control pin. Selects between pin-strap and I2C mode. Refer to Section 8.4.1.

IN_CLKp

Clock differential positive input.

IN_CLKn

Clock differential negative input.

VCC

3.3-V power supply.

SCL/CFG0

I2C Clock/CFG0: When TDP0604 is configured for I2C mode, this pin will function as the

I2C clock. Otherwise, this pin will function as CFG0 as detailed in Table 8-13.

SDA/CFG1

I/O

I2C Data / CFG1: When TDP0604 is configured for I2C mode, this pin will function as the

I2C clock. Otherwise, this pin will function as CFG1 as detailed in Table 8-14.

AC_EN

2-Level (PD)

In pin-strap mode, selects whether high speed transmitters are externally AC or DC-

coupled.

0: DC-coupled

1: AC-coupled

LV_DDC_SCL

I/O

Low voltage side bidirectional DDC clock line. Internally pulled-up to VIO.

LV_DDC_SDA

I/O

Low voltage side bidirectional DDC data line. Internally pulled-up to VIO.

HV_DDC_SDA

I/O

High voltage side bidirectional DDC data line. Pull-up externally to HDMI 5 V.

HV_DDC_SCL

I/O

High voltage side bidirectional DDC clock line. Pull-up externally to HDMI 5 V.

VCC

3.3-V power supply.

TXPRE

4-Level

(PU/PD)

TX pre-emphasis control: In pin-strap mode with limited enabled, this pin controls TX EQ.

Refer to Table 8-11 for available TXPRE settings when operating in pin strap mode. In I2C

mode, TX pre-emphasis is controlled through the registers.

OUT_CLKn

TMDS data clock differential negative output

OUT_CLKp

TMDS data clock differential positive output

HPD_IN

2-Level (PD)

Hot plug detect input from sink side. This pin has an internal pull-down resistor and is

fail-safe.

OUT_D0n

TMDS data 0 differential negative output

OUT_D0p

TMDS data 0 differential positive output

ADDR/EQ0

4-Level

(PU/PD)

Address bit for I2C programming when TDP0604 is configured for I2C mode. Refer to

Table 8-18.

EQ0 pin setting when TDP0604 is configured for pin strap mode; works in conjunction

with EQ1; see Table 8-5 for settings. In I2C mode, EQ settings are controlled through the

registers.

OUT_D1n

TMDS data 1 differential negative output

OUT_D1p

TMDS data 1 differential positive output

TXSWG

4-Level

(PU/PD)

TX output swing control: 4 settings. This pin is only used in pin strap mode. Refer to Table

8-12 for available TX swing settings. In I2C mode, TX output swing is controlled through

the registers.

OUT_D2n

TMDS data 2 differential negative output

OUT_D2p

TMDS data 2 differential positive output

TDP0604

SLLSFJ8 – DECEMBER 2021

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