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TDP0604 Datasheet(PDF) 9 Page - Texas Instruments |
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TDP0604 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 65 page  6.5 Electrical Characteristics (continued) over recommended voltage and operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DDC Buffer (LV_DDC_SCL, LV_DDC_SDA, HV_DDC_SCL, HV_DDC_SDA) VHV_IH High-level input voltage for HV_DDC_SCL and HV_DDC_SDA VIO = 3.3V; VCC = 3.0V 3.3 5.3 V VHV_IL Low-level input voltage for HV_DDC_SCL and HV_DDC_SDA VIO = 3.3V; VCC = 3.0V -0.3 1.6 V VLV_IH High-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.2-V LVCMOS VIO = 1.14V; VCC = 3.3V 0.8 3.6 V VLV_IH High-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.8-V LVCMOS VIO = 1.7V; VCC = 3.3V 1.15 3.6 V VLV_IH High-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 3.3-V LVCMOS VIO = 3.0V; VCC = 3.3V 2.1 3.6 V VLV_IL Low-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.2-V LVCMOS VIO = 1.26V; VCC = 3.3V -0.3 0.082 * VIO V VLV_IL Low-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 1.8-V LVCMOS VIO = 1.9V; VCC = 3.3V -0.3 0.10 * VIO V VLV_IL Low-level input voltage for LV_DDC_SCL and LV_DDC_SDA for 3.3-V LVCMOS VIO = 3.6V; VCC = 3.3V -0.3 0.10 * VIO V ILV_IL_FS Failsafe Input leakage for LV_DDC_SCL and LV_DDC_SDA VCC = 0-V; VIO = VIN = 2.0-V -5.5 5.5 µA IHV_IL_FS Failsafe Input leakage for HV_DDC_SCL and HV_DDC_SDA VIN = 5.3V through 1.5-kΩ; VCC = 0-V; VIO = 0-V; -5 5 µA IHV_IL Input leakage for HV_DDC_SCL and HV_DDC_SDA HV VIN = 5.3V; LV VIN = VIO; -5 5 µA ILV_IL Input leakage for LV_DDC_SCL and LV_DDC_SDA HV VIN = 5.3V; LV VIN = VIO; -5.5 5.5 µA IHV_OL Low-level output current VHV_OL = 0.4V; HDMI5V= 5.3V; Pullup with 1.4-kΩ; VCC = 3.0V; 3.5 mA VHV_OL Low-level output voltage for HV_DDC_SCL and HV_DDC_SDA HDMI5V= 5.3V; Pullup with 1.4-kΩ; VCC = 3.0V; 0.4 V VLV_OL Low-level output voltage for LV_DDC_SCL and LV_DDC_SDA for 1.2- V LVCMOS VCC = 3.0V; VIO = 1.26V 0.2 0.3 V VLV_OL Low-level output voltage for LV_DDC_SCL and LV_DDC_SDA for 1.8- V LVCMOS VCC = 3.0V; VIO = 1.9V 0.3 0.4 V VLV_OL Low-level output voltage for LV_DDC_SCL and LV_DDC_SDA for 3.3- V LVCMOS VCC = 3.0V; VIO = 3.6V 0.6 0.75 V Δ VLV_HYST _1p2V Hysteresis on LV side for 1.2V LVCMOS VIO = 1.2V; VCC = 3.3V; 20 mV Δ VLV_HYST _1p8V Hysteresis on LV side for 1.8V LVCMOS VIO = 1.8V; VCC = 3.3V; 20 mV Δ VLV_HYST _3p3V Hysteresis on LV side for 3.3V LVCMOS VIO = 3.3V; VCC = 3.3V 50 mV Δ VHV_HYST Hysteresis on HV side VIO = 3.3V; VCC = 3.3V; HDMI5V = 4.8V or 5.3V; 500 mV RPULV Internal pull-up resistor to VIO 7450 10000 13000 Ω RPUHV External pull-up resistor to HDMI 5V 1500 1800 2000 Ω CIOHV Capacitance for HV_DDC_SCL and HV_DDC_SDA 12 pF www.ti.com TDP0604 SLLSFJ8 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TDP0604 |
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