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TDP0604 Datasheet(PDF) 3 Page - Texas Instruments |
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TDP0604 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 65 page ![]() 5 Pin Configuration and Functions Thermal Pad 1 VCC 2 TEST1 3 EN 4 5 CTLEMAP_SEL 6 EQ1 7 LINEAR_EN 8 VCC 21 AC_EN 22 SCL/CFG0 23 SDA/CFG1 24 LV_DDC_SCL 25 LV_DDC_SDA 26 HV_DDC_SDA 27 HV_DDC_SCL 28 VCC Not to scale HPDOUT_SEL Figure 5-1. RNQ Package, 40-Pin WQFN (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. VCC 1 P 3.3-V power supply HPDOUT_SEL 2 I 2-Level (PD) HPDOUT_SEL. Selects whether HPD_OUT pin is push/pull, or open-drain. Open-drain is not supported in pin-strap mode. Therefore this pin should be left floating or pull-down to GND. TEST1 3 O Test1. For internal Texas Instruments use only. This pin can be left unconnected. CTLEMAP_SEL 4 I 4-Level (PU/PD) CTLE Map select. When TDP0604 is configured in pin-strap mode, this pin selects the CTLE Map used. Refer to Table 8-7 for details. In I2C mode, CTLE map is determined by registers. LINEAR_EN 5 I 4-Level (PU/PD) In pin-strap mode, selects whether TDP0604 operates in linear or limited redriver mode. Refer to Table 8-4. VCC 6 P 3.3-V power supply. EN 7 I 2-Level (PU) When low, TDP0604 will be held in reset. The IN_D[2:0], IN_CLK, OUT_D[2:0] and OUT_CLK pins will be held in high impedance while EN is low. On rising edge of EN, device will sample 4-level inputs and function based on the sampled state of the pins. This pin has a internal 250k pull-up to VIO. EQ1 8 I 4 Level (PU/PD) EQ1 pin setting when TDP0604 is configured for pin strap mode; Works in conjunction with EQ0; See Table 8-5 for settings. In I2C mode, EQ settings are controlled through the registers. IN_D2p 9 I Channel 2 differential positive input. www.ti.com TDP0604 SLLSFJ8 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TDP0604 |
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